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13.7
Interrupt Vector Table
Interrupt Service Routines (ISRs) are associated with interrupts at a particular priority by
way of the Interrupt Vector Table. The Interrupt Vector Table is an array of ISR entry
points.
When the CPU takes an interrupt, it calculates an address in the Interrupt Vector Table
that corresponds with the priority of the interrupt (the ICR.PIPN bit field). This address is
loaded in the program counter. The CPU begins executing instructions at this address in
the Interrupt Vector Table. The code at this address is the start of the selected ISR.
Depending on the code size of the ISR, the Interrupt Vector Table may only store the
initial portion of the ISR, such as a jump instruction that vectors the CPU to the rest of
the ISR elsewhere in memory.
The Interrupt Vector Table is stored in code memory. The BIV register specifies the base
address of the Interrupt Vector Table. Interrupt vectors are ordered in the table by
increasing priority.
The Base of Interrupt Vector Table register (BIV) stores the base address of the Interrupt
Vector Table. It can be assigned to any available code memory. Its default on power-up
is fixed at 0000 0000
instruction during the initialization phase of the system, before interrupts are enabled.
With this arrangement, it is possible to have multiple Interrupt Vector Tables and switch
between them by changing the contents of the BIV register.
Note: The BIV register is protected by the ENDINIT bit (see chapter describing the
watchdog timer). Modifications should only be done while the interrupt system is
globally disabled (ICR.IE = 0). Also, an ISYNC instruction should be issued after
modifying BIV to ensure completion of this operation before execution of following
instructions.
When interrupted, the CPU calculates the entry point of the appropriate ISR from the
PIPN and the contents of the BIV register. The PIPN is left-shifted by five bits and OR-ed
with the address in the BIV register to generate a pointer into the Interrupt Vector Table.
Execution of the ISR begins at this address. Due to this operation, it is recommended
that bits [12:5] of register BIV are set to 0 (see
register is always 0 and cannot be written to (instructions have to be aligned on even byte
boundaries).
User's Manual
Interrupt, V1.4
. However, the BIV register can be modified using the MTCR
H
Figure
13-2). Note that bit 0 of the BIV
13-15
TC1728
Interrupt System
V1.0, 2011-12
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