Fractional Divider Register - Infineon Technologies TC1728 User Manual

19.3.3.2 Fractional Divider Register

The Fractional Divider Register controls the clock rate of the shift clock
MSC0_FDR
MSC0 Fractional Divider Register
31 30 29 28
DIS EN SUS SUS
CLK HW REQ ACK
rwh rw rh rh
15 14 13 12
DM SC
rw rw
Field Bits
STEP [9:0]
FDIS 10
SM 11
SC [13:12]
DM [15:14]
RESULT [25:16]
SUSACK 28
User's Manual
MSC, V1.37 2009-05
(0C
27 26 25 24
0
r
11 10 9 8
SM FDIS
rw rw
Type Description
rw Step Value
Reload or addition value for RESULT.
rw Freeze Disable
This bit controls the freeze function for this module.
0 Module operates on corrected clock, with
B
reduced modulation jitter.
1 Module operates on uncorrected clock, with
B
full modulation jitter.
rw Suspend Mode
SM selects between granted or immediate suspend
mode.
rw Suspend Control
This bit field determines the behavior of the fractional
divider in suspend mode.
rw Divider Mode
DM selects normal or fractional divider mode.
rh Result Value
Bit field for the addition result.
rh Suspend Mode Acknowledge
Indicates state of SPNDACK signal.
19-68
Micro Second Channel (MSC)
) Reset Value: 0000 0000
H
23 22 21 20
RESULT
rh
7 6 5 4
STEP
rw
TC1728
f
.
MSC0
19 18 17 16
3 2 1 0
V1.0, 2011-12
H