On-Chip Debug Support (Ocds); Overview - Infineon Technologies TC1728 User Manual

32-bit single-chip microcontroller
Table of Contents

Advertisement

16

On-Chip Debug Support (OCDS)

This chapter gives an overview about the debug features of the TC1728 device. This
chapter does not describe the TC1728 debug functionality and capabilities in detail. For
detailed information about the On-Chip Debug Support (OCDS) functionality as required
by tool suppliers please contact local Infineon representatives.
16.1

Overview

TC1728 supports OCDS Level 1 and 3.
OCDS Level 1
The OCDS Level 1 is mainly assigned for system software debugging purposes which
have a demand for low-cost standard debugger hardware.
The OCDS Level 1 is based on a Debug Interface that is used by the external debug
hardware to communicate with the system. The on-chip Cerberus module controls the
interactions between the Debug Interface and the on-chip modules and allows in
particular to access the whole address space of the device. The memory mapped on-
chip debug resources make it possible to trigger on instruction and data addresses as
well as to control user program execution (run/stop, breakpoint, single-step).
OCDS Level 3
The OCDS Level 3 is based on a Multi Core Debug Solution (MCDS) using an Emulation
Device. This device has the following features required for high-end emulation purposes:
Emulation Device is available in the same package variants as TC1728
Higher current consumption due to trace and overlay RAM is the only difference
TriCore program trace
TriCore data trace (no register file trace)
PCP ownership trace
PCP program trace
PCP data write to PRAM trace (no register file trace)
Full visibility of internal peripheral bus (SPB)
Full visibility of Local Memory Bus (LMB)
Time aligned parallel trace of all sources
Breakpoints and watchpoints based on common event generation logic
Magnitude comparators working on instruction pointers and memory addresses:
A <= IP <= B
Masked magnitude comparators working on the data busses: DATA = "xxxx55xx"
Sequential event logic: Counters driven by events and equipped with limit
comparators are used as event sources again for breakpoint or trace qualification
Optimized compression of buffered trace data
Code and data fetch from Emulation Memory
User's Manual
OCDS, V1.5
On-Chip Debug Support (OCDS)
16-1
TC1728
V1.0, 2011-12

Advertisement

Table of Contents
loading

Table of Contents