Clock Control - Infineon Technologies TC1728 User Manual

19.3.3

Clock Control

The MSC0 module is provided with two independent clock signals
f
•
CLC0
This is the module clock that is used inside the MSC kernel for control purposes such
as clocking of control logic and register operations. The frequency of
identical to the system clock frequency
makes it possible to enable/disable
f
•
MSC0
This clock is the module clock that is used inside the MSC for baud rate generation
of the serial upstream and downstream channel. The fractional divider register
MSC0_FDR controls the frequency of
it independent of
Clock Control
f
SYS
Register
MSC0_CLC
MultiCAN
Module
Figure 19-31 MSC0 Module Clock Generation
The following two formulas define the frequency of
1
×
f f -- -
=
MSC0 SYS
n
n
×
f f ------------ -
=
MSC0 SYS
1024
User's Manual
MSC, V1.37 2009-05
f
.
CLC0
MSC0 Clock Generation
Fractional Divider
MSC0_FDR
SR15
with n = 1024 - MSC0_FDR.STEP
with n = 0-1023
Micro Second Channel (MSC)
f
. The clock control register MSC0_CLC
SYS
f
under certain conditions.
CLC0
f
and makes it possible to enable/disable
MSC0
f
MSC0
Register
ECEN
f
CLC0
f
:
MSC0
19-65
TC1728
(Figure 19-31):
f
is always
CLC0
Downstream
Channel
Upstream
URR
Channel
MSC0 Module Kernel
MCA06257
V1.0, 2011-12
(19.3)
(19.4)