Infineon Technologies TC1728 User Manual page 1037

The STM Compare Match Control Register controls the parameters of the compare
logic.
STM_CMCON
STM Compare Match Control Register
31 30 29 28
0
r
15 14 13 12
0
r
Field Bits
MSIZE0 [4:0]
MSTART0 [12:8]
User's Manual
STM, V1.6
(38
27 26 25 24
MSTART1
rw
11 10 9 8
MSTART0
rw
Type Description
rw Compare Register Size for CMP0
This bit field determines the number of bits in register
CMP0 (starting from bit 0) that are used for the
compare operation with the System Timer.
00000
B
00001
B
...
11110
B
11111
B
rw Start Bit Location for CMP0
This bit field determines the lowest bit number of the
56-bit STM that is compared with the content of
register CMP0 bit 0. The number of bits to be
compared is defined by bit field MSIZE0.
00000
B
00001
B
...
10111
B
11000
B
Bit combinations 11001
must not be used.
14-15
) Reset Value: 0000 0000
H
23 22 21 20
0
r
7 6 5 4
0
r
CMP0[0] used for compare operation
CMP0[1:0] used for compare operation
CMP0[30:0] used for compare operation
CMP0[31:0] used for compare operation
STM[0] is the lowest bit number
STM[1] is the lowest bit number
STM[23] is the lowest bit number
STM[24] is the lowest bit number
to 11111
B
TC1728
System Timer (STM)
19 18 17 16
MSIZE1
rw
3 2 1
MSIZE0
rw
are reserved and
B
V1.0, 2011-12
H
0