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15.4.7
Error Correction Code (ECC)
The BMU SRAM is protected by information redundancy based on Error Correction
Codes with a Hamming Distance of 4. The ECC information redundancy applies to the
data bits of each BMU SRAM word.
Limitations with ECC accesses
When the ECC mapping is enabled the memory access limitations described in
in non safety applications" on Page 15-20
information can only be accessed using FPI BTR2 bursts as described in
"ECC information mapping into FPI BTR2 transactions" on Page
base address is 8-byte aligned (FPI_A[2:0] = 3'b000).
ECC Update using FPI BTR 2 Write Burst (when SMACOM .BMURAM = 2)
FPI Addr
@1
FPI WR
Data
71
64
63
...
ECC1
Y[31:0]
...
...
ECC access using FPI BTR 2 Read Burst (when SMACOM .BMURAM = 2)
FPI Addr
@1
FPI RD
Data
Figure 15-11 ECC information mapping into FPI BTR2 transactions
Memory Integrity Error Control
A pair of architecturally visible registers (MIECON, MIECON2) are included to allow
software to control the memory integrity error detection / correction mechanisms. The
existence of the MIECON and MIECON2 registers is architecturally defined. However,
the fields within these registers are implementation specific. The behavior of MIECON2
User's Manual
BMU, V2.6
CTL
@1 + 0x4
Don't care
ECC1
31
8
7
32
31
...
X[31:0]
...
...
@1+4
Don't care
ECC1
31
8
7
apply as well. Therefore the ECC
Don't care
0
31
0
0
...
Offset @1
...
...
Don't care
0
31
0
15-18
TC1728
Bus Monitor Unit (BMU)
"Usage
Figure 15-11
15-18. The burst
V1.0, 2011-12
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