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19.1.2.2 Shift Register Operation
This section describes the SRL and SRH shift register loading.
SRL Shift Register Loading
During the SRL/SRH shift register load operation at the beginning of each downstream
frame transmission, several parameters determine which information is loaded into the
bits of the shift register.
register loading operation. The logic for the SRH shift register loading operation is
equivalent to the one for the SRL register. Its differences in data sources and register
controls are described later in this section.
Downstream Data Register DD
32
DDH
DDH[x]
ALTINL[x]
ESR
ENLx
EMGSTOPMSC
DCH[x]
32
DCH
Downstream Command Register DC
Figure 19-7 SRL Shift Register Data Loading Control
User's Manual
MSC, V1.37 2009-05
Figure 19-7
shows the logic that is implemented for the SRL shift
16
15
DDL
DDL[x]
DSDSL
SLx
2
00
10
11
&
DCL[x]
16
15
DCL
Micro Second Channel (MSC)
0
x = 0-15
DSC
CP
1
0
0
1
CP = 0: Load for Data Frame
CP = 1: Load for Command Frame
0
x = 0-15
19-12
TC1728
To SRL bit x
MCA06233
V1.0, 2011-12
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