Interrupt Registers - Infineon Technologies TC1728 User Manual

14.3.4

Interrupt Registers

The two compare match interrupts of the STM are controlled by the STM Interrupt
Control Register.
STM_ICR
STM Interrupt Control Register
31 30 29 28
15 14 13 12
Field Bits
CMP0EN 0
CMP0IR 1
User's Manual
STM, V1.6
(3C
27 26 25 24
11 10 9 8
0
r
Type Description
rw Compare Register CMP0 Interrupt Enable Control
This bit enables the compare match interrupt with
compare register CMP0.
0 Interrupt on compare match with CMP0 disabled
B
1 Interrupt on compare match with CMP0 enabled
B
rh Compare Register CMP0 Interrupt Request Flag
This bit indicates whether or not a compare match
interrupt request of compare register CMP0 is pending.
CMP0IR must be cleared by software.
0 A compare match interrupt has not been detected
B
since the bit has been cleared for the last time.
1 A compare match interrupt has been detected.
B
CMPIR0 must be cleared by software and can be set by
software, too (see CMPISRR register). After a STM
reset operation, CMP0IR is immediately set as a result
of a compare match event with the reset values of the
STM and the compare registers CMP0.
14-17
) Reset Value: 0000 0000
H
23 22 21
0
r
7 6 5
CMP CMP CMP
1 1
OS IR EN
rw rh
TC1728
System Timer (STM)
20 19 18 17
4 3 2 1
CMP CMP
1 0 0 0
OS IR
rw r rw rh
V1.0, 2011-12
H
16
0
CMP
0
EN
rw