Ocds Level 1 - Infineon Technologies TC1728 User Manual

• LMB OCDS features
– Error recording and service request on bus error
• Multi-Core Break Switch (Cerberus MCBS)
– TriCore, PCP, DMA, break pins and SBCU available as break sources
– TriCore and PCP available as break targets; other parts can be suspended in
addition
– Synchronous stop and restart of the system
– Break to Suspend converter
16.2

OCDS Level 1

The basic principle of the TriCore OCDS Level 1 is that all relevant user and debug
resources are memory mapped. These resources include on-chip memories, CPU core
registers and registers of the peripheral units.
A typical OCDS Level 1 debugging configuration is shown in
two parts:
• The tool software
• The tool access hardware interface adapter
This configuration makes it possible to realize a cost effective debugging environment
that permits comprehensive real-time debugging tasks to be performed.
Tool Software
on PC
Figure 16-2 Typical OCDS Level 1 Hardware Connections
User's Manual
OCDS, V1.5
USB,
Ethernet ,
etc.
Interface
On-Chip Debug Support (OCDS)
Tool
Access
Hardware
16-5
TC1728
Figure 16-2. It comprises
Target Hardware
Product
Chip
Debug_Environment .vsd
V1.0, 2011-12