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13.4.2
Controlling the Duration of Arbitration Cycles
During each arbitration cycle, the rate of information flow between the SRNs and the ICU
can become limited by propagation delays within the TC1728 when it is executing at high
system clock frequencies. At high frequencies, arbitration cycles may require two system
clocks to execute properly. In order to optimize the arbitration scheme at lower system
frequencies, an additional control bit, ICR.CONECYC, is implemented. The default value
of 0 of this bit selects two clock cycles per arbitration cycle. Setting this bit to 1 selects
one
clock
cycle
ICR.CONECYC=´1´ setting is defined in the product data sheetSetting this bit for system
frequencies above the specified limit leads to unpredictable behavior of the interrupt
system. Correct operation is then not guaranteed.
13.5
Entering an Interrupt Service Routine
When an interrupt request from the ICU is pending and all conditions are met such that
the CPU can now service the interrupt request, the CPU performs the following actions
in preparation for entering the designated Interrupt Service Routine (ISR):
1. Upper context of the current task is saved
ICR.CCPN, and the state of the global interrupt enable bit, ICR.IE, are automatically
saved with the PCXI register (bit field PCPN and bit PIE).
2. Interrupt system is globally disabled (ICR.IE is set to 0).
3. Current CPU priority number (ICR.CCPN) is set to the value of ICR.PIPN.
4. PSW is set to a default value:
a) All permissions are enabled, that is, PSW.IO = 10
b) Memory protection is switched to PRS0, that is, PSW.PRS = 0.
c) The stack pointer bit is set to the interrupt stack, that is, PSW.IS = 1.
d) The call depth counter is cleared, the call depth limit is set to 63, that is,
PSW.CDC = 0.
5. Stack pointer, A10, is reloaded with the contents of the Interrupt Stack Pointer, ISP,
if the PSW.IS bit of the interrupted routine was set to 0 (using the user stack);
otherwise it is left unaltered.
6. CPU program counter is assigned with an effective address consisting of the
contents of the BIV register OR-ed with the ICR.PIPN number left-shifted by 5. This
indexes the Interrupt Vector Table entry corresponding to the interrupt priority.
7. Contents at the effective address of the program counter in the Interrupt Vector Table
are fetched as the first instruction of the Interrupt Service Routine (ISR). Execution
continues linearly from there until the ISR branches or exits.
1) Note that, if a context-switch trap occurs while the CPU is in the process of saving the upper context of the
current task, the pending ISR will not be entered, the interrupt request will be left pending, and the CPU will
enter the appropriate trap handling routine instead.
User's Manual
Interrupt, V1.4
per
arbitration
cycle.
The
maximum
1)
. The current CPU priority number,
.
B
13-13
TC1728
Interrupt System
frequency
for
the
V1.0, 2011-12
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