Receive Data Interrupt - Infineon Technologies TC1728 User Manual

19.1.5.4 Receive Data Interrupt

Whenever the upstream channel receives data in registers UDx (x = 0-3), the MSC is
able to generate an interrupt. Three interrupt generation conditions can be selected for
the receive data interrupt:
• Each update of UDx (x = 0-3) generates a receive data interrupt.
• Each update of UDx (x = 0-3) generates a receive data interrupt when the updated
value is not equal 00
• Only an update of register UD3 generates a receive data interrupt.
The selection of the interrupt generation condition is controlled by bit field ICR.RDIE.
Setting ICR.RDIE = 0 disables the receive data interrupt in general. ISR.URDI is the
interrupt status flag that can be set or clear when writing bits ISC.SURDI or ISC.CURDI
with a 1.
Data is received
Data is received and
not equal 00
H
Data is received in UD 3
Figure 19-26 Receive Data Interrupt Control
User's Manual
MSC, V1.37 2009-05
.
H
ICR ISC
RDIE CURDI
SURDI
2
Software
01
Set
10
Hardware
Set
11
19-34
Micro Second Channel (MSC)
Software ISR
Clear
URDI
Set
RDIE = 00
≥1
TC1728
Receive Data
RDI
Interrupt
(to Int. Comp.)
MCA06252_mod
V1.0, 2011-12