Infineon Technologies TC1728 User Manual page 1261

Field Bits
NDBL [7:3]
NDBH [12:8]
ENSELL 13
ENSELH 14
User's Manual
MSC, V1.37 2009-05
Type Description
rw Number of SRL Bits Shifted at Data Frames
NDBL determines the number of shift register low part
(SRL) bits that are shifted out on SO during a data frame.
00000 No SRL bit shifted
B
00001 SRL[0] shifted
B
00010 SRL[1:0] shifted
B
... ...
B
01111 SRL[14:0] shifted
B
10000 SRL[15:0] shifted
B
Other bit combinations are reserved; do not use these bit
combinations.
rw Number of SRH Bits Shifted at Data Frames
NDBH determines the number of shift register high part
(SRH) bits that are shifted out on SO during a data
frame.
00000 No SRH bit shifted; no selection bit is
B
generated, the SRH active phase is
completely skipped.
00001 SRH[0] shifted
B
00010 SRH[1:0] shifted
B
... ...
B
01111 SRH[14:0] shifted
B
10000 SRH[15:0] shifted
B
Other bit combinations are reserved; do not use these bit
combinations.
rw Enable SRL Active Phase Selection Bit
This bit determines whether a low level selection bit is
inserted at the beginning of a data frame's SRL active
phase.
0 No selection bit inserted.
B
1 Low level selection bit inserted.
B
rw Enable SRH Active Phase Selection Bit
This bit determines whether a low level selection bit is
inserted at the beginning of a data frame's SRH active
phase.
0 No selection bit inserted.
B
1 Low level selection bit inserted.
B
19-42
Micro Second Channel (MSC)
TC1728
V1.0, 2011-12