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17.1.4.1 Synchronous Transmission
Synchronous transmission begins within four state times after data has been loaded into
TBUF, provided that CON.R is set and CON.REN = 0 (half-duplex, no reception), with
one exception: in Loop-back Mode (bit CON.LB set), CON.REN must be set for reception
of the transmitted byte. Data transmission is double-buffered. When the transmitter is
idle, the transmit data loaded into TBUF is immediately moved to the transmit shift
register, thus freeing TBUF for the next data to be sent. This is indicated by the transmit
buffer interrupt request line TBIR being activated. TBUF may now be loaded with the
next data, while transmission of the previous one continues. The data bits are
transmitted synchronously with the shift clock. After the bit time for the 8
TXD and RXD will be set to high level, the transmit interrupt request line TIR is activated,
and serial data transmission stops.
Note: The dedicated GPIO device pins that are connected to TXD and RXD must be
configured by software as alternate data outputs in order to provide the shift clock
and the output data during synchronous transmission.
17.1.4.2 Synchronous Reception
Synchronous reception is initiated by setting bit CON.REN = 1. If bit CON.R = 1, the data
applied at RXD is clocked into the receive shift register synchronously to the clock which
is output at TXD. After the 8
register are transferred to the receive data buffer RBUF, the receive interrupt request line
RIR is activated, the receiver enable bit CON.REN is reset, and serial data reception
stops.
Synchronous reception is stopped by clearing bit CON.REN. Any byte that is currently
being received is completed, including the generation of the receive interrupt request
and an error interrupt request, if appropriate. Writing to the transmit buffer register while
a reception is in progress has no effect on reception and will not start a transmission.
If a previously received byte has not been read out of the receive buffer register by the
time the reception of the next byte is complete, both the error interrupt request line EIR
and the overrun error status flag CON.OE will be activated/set, provided that the overrun
check has been enabled by bit CON.OEN.
Note: The dedicated GPIO device pin that is connected to TXD must be configured by
software as alternate data output in order to provide the shift clock. The dedicated
GPIO device pin that is connected to RXD must be configured by software as input
during synchronous reception.
User's Manual
ASC, V1.3 2007-11
Asynchronous/Synchronous Serial Interface (ASC)
th
bit has been shifted in, the contents of the receive shift
17-10
TC1728
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data bit, both
V1.0, 2011-12
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