Queued Ssc Mode - Infineon Technologies TC1728 User Manual

18.1.2.11 Queued SSC Mode

In queued SSC mode, the enable/disable control of the SSC is possible by two bit
locations, one control bit in register CON and one additional control bit in register
SSOTC. This double-enable control capability allows control and data operations of the
SSC to be completely handled by a DMA controller.
The bits for queued SSC mode are:
• Bit SSCTC.QSMEN: Queued SSC Mode Enable
• Bit SSCTC.EN: Enable SSC (functionality identical with bit CON.EN)
Table 18-2 Queued SSC Mode Control
Write SSOTC Register
Bit QSMEN Bit EN
0 X
1 0
1
Note: Both register bits, CON.EN and SSOTC.EN, control one common flip-flop for
enable/disable control.
Figure 18-13 shows how the Queued SSC Mode control logic. Reading SSOTC returns
the state of CON.EN for SSOTC.EN. Writing to SSOTC with QSMEN = 1, sets CON.EN
if SSOTC.EN is written with 1 and clears CON.EN if SSOTC.EN is written with 0.
Compared to the timing parameters stored in register SSOTC (LEAD, TRAIL, INACT,
and SLSO7MOD), the Queued SSC Mode control bits QSMEN and EN are a not latched
and directly control the receive/transmit functionality. But note that CON.EN should only
be cleared by software (either by a CON or SSOTC write operation) while no transfer is
in progress (STAT.BSY = 0).
User's Manual
SSC, V1.41 2010-06
Synchronous Serial Interface (SSC)
SSC Module Enable/Disable Control
Enable/disable control of SSC is only possible via bit
CON.EN (queued SSC mode disabled).
Enable/disable control of
SSC is possible via bits
SSOTC.EN and
CON.EN (queued SSC
mode enabled).
18-24
TC1728
SSC is disabled
SSC is enabled
V1.0, 2011-12