Downstream Counter And Enable Signals - Infineon Technologies TC1728 User Manual

19.1.2.4 Downstream Counter and Enable Signals

During downstream channel operation, a 7-bit downstream counter DSS.DC is counting
FCL shift clock periods. With the loading of the shift register, the downstream counter is
reset to 00 and started for counting up to the end of the downstream frame (end of
H
passive phase).
In Triggered Mode, the downstream counter stops counting at the end of the passive
phase and waits until a new downstream frame is started.
In Repetition Mode, the downstream counter does not stop at the end of the passive
phase but is reset and starts counting up again with the next frame, independently
whether a data frame, command frame, or passive time frame is started as next frame.
Figure 19-12 shows an example of downstream channel data frame transmission. In this
example, the selection bit for the SRL active frame is enabled (ENSELL = 1), and the
selection bit for the SRH active frame is disabled (ENSELH = 0). With loading of the shift
register SRL/SRH, the downstream counter is reset and then starts counting up with
each FCL clock until the end of the passive phase. ENL is set to high level at the
beginning of the SRL active frame selection bit.
SRL/SRH
Loading
State of
DSS.DC
FCL
SO
ENL
ENH
Figure 19-12 Shift Clock Counting: Data Frame with ENSELL = 1 and ENSELH = 0
User's Manual
MSC, V1.37 2009-05
m
3
2
1
0
0
SRL.0 SRL.1
SRL Active Phase
Micro Second Channel (MSC)
m+4
m+2 m+3
m+1
t
FCL
SRL.m SRH.0 SRH.1
SRH Active Phase
Downstream Frame
19-19
TC1728
DC
max
SRH.n
Passive
Phase
MCT06238
V1.0, 2011-12