Infineon Technologies XC82x User Manual

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8-Bit

XC82x

8-Bit Single-Chip Microcontroller

User's Manual

V1.0 2010-02

M i c r o c o n t r o l l e r s

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Page 1 8-Bit XC82x 8-Bit Single-Chip Microcontroller User’s Manual V1.0 2010-02 M i c r o c o n t r o l l e r s...
Page 2 Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life.
Page 3 8-Bit XC82x 8-Bit Single-Chip Microcontroller User’s Manual V1.0 2010-02 M i c r o c o n t r o l l e r s...
Page 4 XC82x XC82x User’s Manual Revision History: V1.0 2010-02 Previous Versions: Page Subjects (major changes since last revision) – We Listen to Your Comments Is there any information in this document that you feel is wrong, unclear or missing? Your feedback will help us to continuously improve the quality of this document.
Page 5 XC82x Feature List ........
Page 6 XC82x 3.4.5.5 ADC Registers ........3-19 [1] 3.4.5.6...
Page 7 XC82x 6.2.2 The Selection of Working Modes ......6-8 [1] 6.2.2.1 Receiving the Header Block ......6-8 [1] 6.2.2.2...
Page 8 XC82x 8.4.1 Watchdog Timer Registers ....... 8-7 [1] Interrupt System ........9-1 [1] Interrupt Sources .
Page 9 XC82x 10.6.1 NMI request from OCDS ....... 10-12 [1] 10.6.2 General NMI control by OCDS .
Page 10 XC82x 13.2 System Information ........13-1 [1] 13.2.1...
Page 11 XC82x 15.5.2 Mode 3: Timer Mode with External Clock ....15-4 [1] 15.6 Power Saving Mode Option ....... . 15-5 [1] 15.7...
Page 12 XC82x 17.7 Software Reset ......... 17-7 [1] 17.8...
Page 13 XC82x 19.4.1 LED Pin Assignment and Current Capability ....19-10 [1] 19.5 Touchpad Sensing ........19-11 [1] 19.5.1...
Page 14 XC82x 20.3.8.3 Capture/Compare Registers ......20-46 [1] 20.3.8.4 Capture/Compare Shadow Registers ....20-47 [1] 20.3.8.5...
Page 15 XC82x 20.10.2 General Registers ........20-127 [1] 20.10.2.1...
Page 16 XC82x 22.6 Flash Program Subroutine ....... . . 22-7 [1] 22.7...
Page 17 2.5 V to 5.5 V. In addition, the XC82x is equipped with embedded Flash memory to offer high flexibility in development and ramp-up. The XC82x memory protection strategy features read-out protection of user intellectual property (IP).
Page 18 XC82x Introduction XC82x Feature List The following list summarizes the main features of the XC82x: • High performance XC800 Core – compatible to standard 8051 Core – two clocks per machine cycle architecture (for memory access without wait state) – two data pointers •...
Page 19: Pin Configuration
On-chip OSC LED and Touch Sense Controller 1) Includes 1-Kbyte monitor ROM Figure 1-2 XC82x Block Diagram Pin Configuration Figure 1-3 shows the pin configuration of XC824 in DSO-20 package and Figure 1-4 shows the pin configuration of XC822 in TSSOP-16 package.
Page 20 XC82x Introduction P0.5/RXD_0/RTCCLK/MTSR_0/MRST_1/ P0.6/SPD_0/RXD_1/SDA_0/MTSR_1/ EXINT0_0/LINE5/TSIN5/COUT62_1/TXD_3/ MRST_0/EXINT0_1/T2EX_0/LINE6/TSIN6/ COL1_1/EXF2_2 TXD_0/COL2_1/COLA_1 P0.4/T2EX_1/SCL_0/SCK_0/EXINT1_0/ P1.4/EXINT5/COL4/COUT62_0/ CTRAP_1/LINE4/TSIN4/EXF2_0/COL0_1/ COUT63_1 COL3_1/COLA_2 P0.3/CC60_1/SDA_1/CTRAP_0/ P1.5/CC62_0/COL5/COLA_0 LINE3/TSIN3 P2.3/CCPOS0_2/CTRAP_2/T2_2/ P0.2/T1_0/CC62_1/SCL_1/CCPOS2_0/ EXINT3/AN3 LINE2/TSIN2 P2.2/CCPOS2_1/T12HR_3/T13HR_3/ P0.1/T0_0/CC61_1/MTSR_3/MRST_2/ SCK_1/T1_1/EXINT2/AN2 T13HR_0/CCPOS1_0/LINE1/TSIN1 XC824 P2.1/CCPOS1_1/RXD_3/MTSR_4/T0_1/ P0.0/T2_0/T13HR_1/MTSR_2/MRST_3/ EXINT1_1/AN1 T12HR_0/CCPOS0_0/LINE0/TSIN0/COUT61_1 P2.0/CCPOS0_1/T12HR_2/T13HR_2/ T2EX_3/T2_1/EXINT0_3/AN0 P1.0/SPD_1/RXD_2/T2EX_2/EXINT0_2/ COL0_0/COUT60_0/TXD_1 P1.1/CC60_0/COL1_0/TXD_2 P1.2/EXINT4/COL2_0/COUT61_0/ P1.3/CC61_0/COL3_0/CC61_0/EXF2_1 COUT63_0 Figure 1-3 XC824 (DSO-20 package) Pin Configuration (Top View) User’s Manual...
Page 21 Pull-up device enabled only (PU) • Pull-down device enabled only (PD) • High impedance with both pull-up and pull-down devices disabled (Hi-Z) The functions and default states of the XC82x external pins are provided in Table 1-1. User’s Manual V1.0, 2010-02...
Page 22 XC82x Introduction Table 1-1 Pin Definitions and Functions for XC82x Symbol Pin Type Reset Function Number State DSO20/ TSSOP16 Port 0 Port 0 is a bidirectional general purpose I/O port. It can be used as alternate functions for LEDTSCU, Timer 0, 1 and 2, SSC, CCU6, IIC, SPD and UART.
Page 23 XC82x Introduction Table 1-1 Pin Definitions and Functions for XC82x Symbol Pin Type Reset Function Number State DSO20/ TSSOP16 P0.2 17/14 Hi-Z T1_0 Timer 1 Input CC62_1 Input/Output of Capture/Compare channel 1 SCL_1 IIC Clock Line CCPOS2_0 CCU6 Hall Input 2...
Page 24 XC82x Introduction Table 1-1 Pin Definitions and Functions for XC82x Symbol Pin Type Reset Function Number State DSO20/ TSSOP16 P0.5 20/1 Hi-Z RXD_0 UART Receive Input RTCCLK RTC External Clock Input MTSR_0 SSC Master Transmit Output/ Slave Receive Input MRST_1...
Page 25 XC82x Introduction Table 1-1 Pin Definitions and Functions for XC82x Symbol Pin Type Reset Function Number State DSO20/ TSSOP16 Port 1 Port 1 is a bidirectional general purpose I/O port. It can be used as alternate functions for CCU6, LEDTSCU, SPD, UART and Timer 2.
Page 26 XC82x Introduction Table 1-1 Pin Definitions and Functions for XC82x Symbol Pin Type Reset Function Number State DSO20/ TSSOP16 P1.4 Hi-Z EXINT5 External Interrupt Input 5 COL4 LED Column 4 COUT62_0 Output of Capture/Compare channel 2 COUT63_1 Output of Capture/Compare channel 3 P1.5...
Page 27 XC82x Introduction Table 1-1 Pin Definitions and Functions for XC82x Symbol Pin Type Reset Function Number State DSO20/ TSSOP16 P2.1 Hi-Z CCPOS1_1 CCU6 Hall Input 1 RXD_3 UART Receive Input MTSR_4 Slave Receive Input T0_1 Timer 0 Input EXINT1_1 External Interrupt Input 1...
Page 28 Introduction Chip Identification Number Each device variant of XC82x is assigned an unique chip identification number to allow easy identification of one device variant from the others. The differentiation is based on the product, variant type and device step information.
Page 29: Text Conventions
Text Conventions This document uses the following text conventions for named components of the XC82x: • Functional units of the XC82x are shown in upper case. For example: “The SSC can be used to communicate with shift registers.” • Pins using negative logic are indicated by an overbar. For example: “A reset input pin RESET is provided for the hardware reset.”...
Page 30 Undefined Certain bit combinations in a bit field can be labeled “Reserved”, indicating that the behavior of the XC82x is undefined for that combination of bits. Setting the register to undefined bit combinations may lead to unpredictable results. Such bit combinations are reserved.
Page 31 XC82x Introduction Table 1-3 Acronyms (cont’d) Acronym Description Controller Area Network CCU6 Capture/Compare Unit 6 Clock Generation Unit CORDIC Cordinate Rotation Digital Computer Central Processing Unit Device Access Port Differential Non-Linearity error Error Correction Code Embedded Voltage Regulator Fractional Divider...
Page 32 XC82x Introduction Table 1-3 Acronyms (cont’d) Acronym Description Program Status Word Pulse Width Modulation Random Access Memory Read-Only Memory Real-Time Clock System Control Unit of the device Special Function Register Single Pin DAP Serial Peripheral Interface Synchronous Serial Channel Total Unadjusted Error...
Page 33 XC82x XC800 Core XC800 Core This chapter describes the XC800 Core. Overview The XC800 Core is a complete, high performance CPU core that is functionally upward compatible to the 8051. While the standard 8051 core is designed around a 12-clock machine cycle, the XC800 Core uses a two-clock period machine cycle.
Page 34 XC82x XC800 Core Internal Data Memory Core SFRs Register Interface External SFRs External Data Memory 16-bit Registers & Memory Interface Program Memory Opcode & Immediate Multiplier / Divider Registers Opcode Decoder Timer 0 / Timer 1 Clocks State Machine &...
Page 35: Data Pointer
XC82x XC800 Core The access control unit is responsible for the selection of the on-chip memory resources. The interrupt requests from the peripheral units are handled by the interrupt controller unit. SFRs of the CPU The XC800 Core registers occupy direct Internal Data Memory space locations in the...
Page 36 XC82x XC800 Core Program Status Word Register Reset Value: 00 RMAP: X, PAGE: X Field Bits Type Description Parity Flag Set/cleared by hardware after each instruction to indicate an odd/even number of “one” bits in the accumulator, i.e. even parity.
Page 37 XC82x XC800 Core 2.3.6 Extended Operation Register (EO, A2 The instruction set includes an additional instruction MOVC @(DPTR++),A which writes to program memory implemented as RAM. This instruction may be used both to download code into the program memory when the CPU is initialized and subsequently, to provide software updates.
Page 38: Interrupt Registers
XC82x XC800 Core 2.3.7 Power Control Register (PCON, 87 The PCON register provides control for entering idle mode, baud rate control for UART in mode 2, as well as two general purpose flags. The XC800 Core has two power-saving modes: idle mode and power-down mode. The idle mode can be entered via the PCON register.
Page 39: Timer Registers
XC82x XC800 Core SFRs of The Core Peripherals 2.4.1 Timer Registers Two 16-bit timers are provided - Timer 0 (T0) and Timer 1 (T1). Refer to Timer 0 and Timer 1 chapter for details of the timer registers. 2.4.2 UART Registers The UART uses three SFRs - PCON, SCON and SBUF.
Page 40: Instruction Timing
XC82x XC800 Core Instruction Timing A CPU machine cycle comprises two input clock periods, referred to as Phase 1 (P1) and Phase 2 (P2), that correspond to two different CPU states. A CPU state within an instruction is referenced by the machine cycle and state number, e.g., C2P1 means the first clock period within machine cycle 2.
Page 41 XC82x XC800 Core Instruction Timing Examples CCLK Read next opcode (without wait state) C1P1 C1P2 next instruction Read next opcode (one wait cycle) C1P1 C1P2 W AIT W AIT next instruction (a) 1-byte, 1-cycle instruction, e.g. INC A Read 2...
Page 42 XC82x XC800 Core Table 2-1 lists all the instructions supported by the XC800 Core. Instructions are 1, 2 or 3 bytes long as indicted in the ‘Bytes’ column. Each instruction takes 1, 2 or 4 machine cycles to execute (with no wait cycle). The table gives two values for the number of machine cycles required by each instruction.
Page 43 XC82x XC800 Core Table 2-1 Instruction Table (cont’d) Mnemonic Hex Code Bytes Machine Machine Cycles Cycles (one wait state (no wait state) MUL AB DIV AB DA A LOGICAL ANL A,Rn 58-5F ANL A,dir ANL A,@Ri 56-57 ANL A,#data ANL dir,A...
Page 44 XC82x XC800 Core Table 2-1 Instruction Table (cont’d) Mnemonic Hex Code Bytes Machine Machine Cycles Cycles (one wait state (no wait state) DATA TRANSFER MOV A,Rn E8-EF MOV A,dir MOV A,@Ri E6-E7 MOV A,#data MOV Rn,A F8-FF MOV Rn,dir A8-AF...
Page 45 XC82x XC800 Core Table 2-1 Instruction Table (cont’d) Mnemonic Hex Code Bytes Machine Machine Cycles Cycles (one wait state (no wait state) BOOLEAN CLR C CLR bit SETB C SETB bit CPL C CPL bit ANL C,bit ANL C,/bit ORL C,bit...
Page 46 XC82x XC800 Core Table 2-1 Instruction Table (cont’d) Mnemonic Hex Code Bytes Machine Machine Cycles Cycles (one wait state (no wait state) CJNE A,dir,rel CJNE A,#d,rel CJNE Rn,#d,rel B8-BF CJNE @Ri,#d,rel B6-B7 DJNZ Rn,rel D8-DF DJNZ dir,rel MISCELLANEOUS ADDITIONAL INSTRUCTIONS...
Page 47: Memory Organization
XC82x Memory Organization Memory Organization The XC82x CPU operates in the following five address spaces: • 8 Kbytes of Boot ROM program memory • 256 bytes of internal RAM data memory • 256 bytes of XRAM memory (XRAM can be read/written as program memory or external data memory) •...
Page 48: Program Memory
Memory Organization Program Memory The code space is theorectically 64 KBytes. However, only access to defined program memory (as shown in memory map figure) is supported. For XC82x, defined code space is occupied by on-chip memories. Data Memory The data space consists of an internal and external data space. Access to internal and external data space are distinguished by different sets of instruction opcodes.
Page 49 On-Chip XRAM Address Higher Order (F2 Reset Value: F0 RMAP: 0, PAGE: 3 ADDRH Field Bits Type Description ADDRH [7:0] Higher Order of On-chip XRAM Address The value for XC82x is F0 User’s Manual V1.0, 2010-02 Memory Organization, V 0.1...
Page 50: Special Function Registers
Memory Organization Memory Protection Strategy The memory protection strategy in XC82x prevents unauthorized read out of critical data and user IP from Flash memory by blocking all external access to the device. This is achieved by using the Boot Mode Index (BMI) to control the boot options such that once the BMI is programmed to enter user mode (productive), it is not allowed to enter the other boot modes without an erase of the BMI by the user code.
Page 51 XC82x Memory Organization Standard Area (RMAP = 0) Module 1 SFRs SYSCON0.RMAP Module 2 SFRs Module n SFRs SFR Data (to/from CPU) Mapped Area (RMAP = 1) Module (n+1) SFRs Module (n+2) SFRs Module m SFRs Direct Internal Data Memory Address...
Page 52: System Control Register
XC82x Memory Organization 3.4.1.1 System Control Register 0 The SYSCON0 register contains the bit to select the SFR mapping. SYSCON0 System control Register 0 Reset Value: 00 RMAP: X, PAGE: X RMAP Field Bits Type Description RMAP Special Function Register Map Control Accessed to non-mapped (standard) special function register area.
Page 53 Address extension is further performed at the module level by paging. With the address extension by mapping, the XC82x has a 256-SFR address range. However, this is still less than the total number of SFRs needed by the on-chip peripherals. To meet this requirement, some peripherals have a built-in local address extension mechanism for increasing the number of addressable SFRs.
Page 54 The use of only write operations makes the system simpler and faster. Consequently, this mechanism significantly improves the performance of short interrupt routines. The XC82x supports local address extension for: • Parallel Ports •...
Page 55 XC82x Memory Organization 3.4.2.1 Page Register The page register has the following definition: MOD_PAGE Page Register for module MOD Reset Value: 00 STNR PAGE Field Bits Type Description PAGE [2:0] Page Bits When written, the value indicates the new page.
Page 56: Bit-Addressing
XC82x Memory Organization Field Bits Type Description [7:6] Operation Manual page mode. The value of STNR is ignored and PAGE is directly written. New page programming with automatic page saving. The value written to the bit positions of PAGE is stored. In parallel, the previous contents of PAGE are saved in the storage bit field STx indicated by STNR.
Page 57 XC82x Memory Organization 3.4.4 Bit Protection Scheme The bit protection scheme prevents direct software writing of selected bits (i.e., protected bits) using the PASSWD register. When the bit field MODE is 11 , writing 10011 to the bit field PASS opens access to writing of all protected bits, and writing 10101 to the bit field PASS closes access to writing of all protected bits.
Page 58 XC82x Memory Organization Field Bits Type Description MODE [1:0] Bit Protection Scheme Control bits Scheme disabled - direct access to the protected bits is allowed. Scheme enabled - the bit field PASS has to be written with the passwords to open and close the access to protected bits.
Page 59: Cpu Registers
XC82x Memory Organization 3.4.5 XC82x Register Overview The SFRs of the XC82x are organized into groups according to their functional units. The contents (bits) of the SFRs are summarized in Section 3.4.5.1 Section 3.4.5.12. Note: The addresses of the bit addressable SFRs appear in bold typeface.
Page 60 XC82x Memory Organization Table 3-1 CPU Register Overview (cont’d) Addr Register Name A8 H IEN0 Reset: 00 H Bit Field Interrupt Enable Register 0 Type B8 H Reset: 00 H Bit Field Interrupt Priority Register Type B9 H Reset: 00 H...
Page 61: System Control Registers
XC82x Memory Organization Table 3-2 MDU Register Overview (cont’d) Addr Register Name B3 H Reset: 00 H Bit Field DATA MDU Result Register 1 Type B4 H Reset: 00 H Bit Field DATA MDU Operand Register 2 Type B4 H...
Page 62 XC82x Memory Organization Table 3-3 SCU Register Overview (cont’d) Addr Register Name F2 H IRCON0 Reset: 00 H Bit Field EXINT EXINT EXINT EXINT EXINT Interrupt Request Register 0 Type F3 H IRCON1 Reset: 00 H Bit Field ADCS ADCS...
Page 63 XC82x Memory Organization Table 3-3 SCU Register Overview (cont’d) Addr Register Name EE H MODPISEL3 Reset: 00 H Bit Field IST13HR1 IST12HR1 CTRAPIS Peripheral Input Select Register Type F2 H XADDRH Reset: F0 H Bit Field ADDRH On-chip XRAM Address Higher...
Page 64: Port Registers
XC82x Memory Organization Table 3-3 SCU Register Overview (cont’d) Addr Register Name F7 H FEAH Reset: 00 H Bit Field ECCERRADDR Flash Error Address Register Type High 3.4.5.4 Port Registers The Port SFRs can be accessed in the standard memory area (RMAP = 0).
Page 65: Adc Registers
XC82x Memory Organization Table 3-4 Port Register Overview (cont’d) Addr Register Name 80 H P0_ALTSEL0 Reset: 00 H Bit Field P0 Alternate Select 0 Register Type 85 H P0_ALTSEL2 Reset: 00 H Bit Field P0 Alternate Select 2 Register Type...
Page 66 XC82x Memory Organization Table 3-5 ADC Register Overview (cont’d) Addr Register Name CE H ADC_INPCR0 Reset: 00 H Bit Field Input Class 0 Register Type CF H ADC_LCBR1 Reset: B0 H Bit Field BOUND1 Limit Check Boundary Register 1 Type...
Page 67 XC82x Memory Organization Table 3-5 ADC Register Overview (cont’d) Addr Register Name CB H ADC_RCR1 Reset: 00 H Bit Field VFCT DLPF DRCT Result Control Register 1 Type CC H ADC_RCR2 Reset: 00 H Bit Field VFCT DLPF DRCT Result Control Register 2...
Page 68 XC82x Memory Organization Table 3-5 ADC Register Overview (cont’d) Addr Register Name CC H ADC_CRMR1 Reset: 00 H Bit Field LDEV CLRP SCAN ENSI ENTR ENGT Conversion Request Mode Register 1 Type CD H ADC_QMR0 Reset: 00 H Bit Field...
Page 69 XC82x Memory Organization 3.4.5.6 LEDSCU Registers The LEDSCU SFRs can be accessed in the standard memory area (RMAP = 0). Table 3-6 LEDSCU Register Overview Addr Register Name RMAP = 0 97 H LTS_GLOBCTL0 Reset: 00 H Bit Field LD_EN TS_EN...
Page 70: Rtc Registers
XC82x Memory Organization 3.4.5.7 RTC Registers The RTC SFRs can be accessed in the standard memory area (RMAP = 0). Table 3-7 RTC Register Overview Addr Register Name RMAP = 0 95 H RTC_RTCON Reset: 00 H Bit Field SFRT...
Page 71 XC82x Memory Organization Table 3-7 RTC Register Overview (cont’d) Addr Register Name E9 H RTC_RTCCR1 Reset: 00 H Bit Field CC_SECONDS Real-Time Clock Type Compare/Capture Register 1 Modes 0 and 2 E9 H RTC_RTCCR1 Reset: 00 H Bit Field CC_VAL...
Page 72 XC82x Memory Organization 3.4.5.8 Timer 2 Registers The Timer 2 SFRs can be accessed in the standard memory area (RMAP = 0). Table 3-8 T2 Register Overview Addr Register Name RMAP = 0 C0 H T2_T2CON Reset: 00 H Bit Field...
Page 73 XC82x Memory Organization Table 3-9 CCU6 Register Overview (cont’d) Addr Register Name 9D H CCU6_TCTR4H Reset: 00 H Bit Field T13R T13R Timer Control Register 4 High Type 9E H CCU6_MCMOUTSL Reset: 00 H Bit Field STRM MCMPS Multi-Channel Mode Output Shadow...
Page 74 XC82x Memory Organization Table 3-9 CCU6 Register Overview (cont’d) Addr Register Name 9D H CCU6_T12PRH Reset: 00 H Bit Field T12PVH Timer T12 Period Register High Type 9E H CCU6_T13PRL Reset: 00 H Bit Field T13PVL Timer T13 Period Register Low...
Page 75 XC82x Memory Organization Table 3-9 CCU6 Register Overview (cont’d) Addr Register Name 9D H CCU6_IENH Reset: 00 H Bit Field ENT1 ENT1 Capture/Compare Interrupt Enable IDLE TRPF Register High Type 9E H CCU6_INPL Reset: 40 H Bit Field INPCHE INPCC62...
Page 76 XC82x Memory Organization Table 3-9 CCU6 Register Overview (cont’d) Addr Register Name 9C H CCU6_ISL Reset: 00 H Bit Field ICC62 ICC62 ICC61 ICC61 ICC60 ICC60 Capture/Compare Interrupt Status Register Low Type 9D H CCU6_ISH Reset: 00 H Bit Field...
Page 77 XC82x Memory Organization 3.4.5.10 SSC Registers The SSC SFRs can be accessed in the standard memory area (RMAP = 0). Table 3-10 SSC Register Overview Addr Register Name RMAP = 0 AA H SSC_CONL Reset: 00 H Bit Field Control Register Low...
Page 78 XC82x Memory Organization Table 3-11 IIC Register Overview (cont’d) Addr Register Name DD H IIC_BRCR Reset: 00 H Bit Field PREDIV Baud Rate Control Register Type DE H IIC_ADDRX Reset: 00 H Bit Field SLAX Extended Slave Address Type Register...
Page 79 XC82x Memory Organization Table 3-12 OCDS Register Overview (cont’d) Addr Register Name EB H MMWR1 Reset: 00 H Bit Field MMWR1 Monitor Work Register 1 Type EC H MMWR2 Reset: 00 H Bit Field MMWR2 Monitor Work Register 2 Type User’s Manual...
Page 80: Flash Memory
Flash Memory Flash Memory The XC82x has an embedded user-programmable non-volatile Flash memory that allows for fast and reliable storage of user code and data. It is operated with a single 2.5 V supply from the Embedded Voltage Regulator (EVR) and does not require additional programming or erasing voltage.
Page 81 4 Kbytes 0000 4 Kbytes Figure 4-1 Flash Memory Map For the XC82x, only a single 4-Kbyte Flash bank, Bank 0, is available. The Flash bank is mapped to two program memory address spaces 0000 - 0FFF and A000 - AFFF The double-mapping of the Flash banks is intended to facilitate software coding.
Page 82 XC82x Flash Memory Sector 9: 128-byte Sector 8: 128-byte Sector 7: 128-byte Sector 6: 128-byte Sector 5: 256-byte Sector 4: 256-byte Sector 3: 512-byte Sector 2: 512-byte Sector 1: 1-Kbyte Sector 0: 1-Kbyte 1x Flash Bank Figure 4-2 Flash Bank Sectorization Sector Partitioning in each 4-Kbyte Flash bank: •...
Page 83 XC82x Flash Memory data (representing the EEPROM data) is copied to the bottom area of the next sector and the last sector is then erased. This round robin procedure, using multifold replications of the emulated EEPROM size, significantly increases the Flash endurance.
Page 84 XC82x Flash Memory Wordline Address The wordline (WL) addresses of Flash Bank 0 are given in Figure 4-3. Byte 31 Byte 2 Byte 1 Byte 0 Byte 31 Byte 2 Byte 1 Byte 0 0FFF …………………………… .. 0FE2 0FE1 0FE0 AFFF ……………………………...
Page 85 XC82x Flash Memory A WL address can be calculated as follow: × n, with 0 ≤ n ≤ 127 for Flash Bank 0 0000 /A000 + 20 (4.1) Only one out of all the wordlines in the Flash banks can be programmed each time. The maximum/minimum program width of each WL is 32 bytes.
Page 86 XC82x Flash Memory 32 bytes (1 WL) 16 bytes 16 bytes 0000 ….. 0000 0000 ….. 0000 Program 1 0000 ….. 0000 1111 ….. 1111 0000 ….. 0000 1111 ….. 1111 1111 ….. 0000 0000 ….. 0000 Program 2 Note: A Flash memory cell can be programmed 1111 …..
Page 87: Operating Modes
XC82x Flash Memory Operating Modes The Flash operating modes for each bank are shown in Figure 4-5. Sector(s) Erase Ready-to-Read Program Call of Call of Flash erase routine Flash program routine or by BSL or by BSL Power-Down System Power-Down...
Page 88: Error Detection And Correction
XC82x Flash Memory Error Detection and Correction The 8-bit data from the CPU is encoded with an Error Correction Code (ECC) before being stored in the Flash memory. During a read access, data is retrieved from the Flash memory and decoded for dynamic error detection and correction.
Page 89 XC82x Flash Memory 4.5.1 Flash Error Address Register The FEAL and FEAH registers together store the 16-bit Flash address at which the ECC error occurs. The bit field PAGE of SCU_PAGE register must be programmed before accessing these registers. FEAL...
Page 90: In-System Programming
XC82x Flash Memory In-System Programming In-System Programming (ISP) of the Flash memory is supported via the Boot ROM- based Boot-loader (BSL), allowing a blank microcontroller device mounted onto an application board to be programmed with the user code, and also a previously programmed device to be erased then reprogrammed without removal from the board.
Page 91: In-Application Programming
XC82x Flash Memory In-Application Programming In some applications, the Flash contents may need to be modified during program execution. In-Application Programming (IAP) is supported so that users can program or erase the Flash memory from their Flash user program by calling some subroutines in...
Page 92: Flash Programming
XC82x Flash Memory 4.7.1 Flash Programming Each call of the Flash program subroutine allows the programming of 32 bytes of data into the selected wordline (WL) of the Flash bank. Before calling this subroutine, the user must ensure that the 32-byte WL contents are stored incrementally in the IRAM, starting from the address specified in R5 of the current register bank.
Page 93 Each complete erase operation on a Flash bank requires approximately 100 ms, during which read and program operations on the Flash bank cannot be performed. For the XC82x, provision has been made to allow an on-going background Flash erase operation to be interrupted so that higher priority tasks such as reading/programming of critical data from/to the Flash bank can be performed.
Page 94 Flash Read Mode Status subroutine to check if the abort erase operation has been completed. When the selected bank is already in Read Mode, it indicates that the abort erase operation has been completed. 1) Refer to XC82x Data Sheet for Flash data profile User’s Manual 4-15 V1.0, 2010-02...
Page 95 XC82x Flash Memory 4.7.4 Flash Read Mode Status Besides the Flash program and erase subroutines, a subroutine to check the ready-to- read mode status of the Flash Bank is additionally provided. Before calling this subroutine, the user must ensure that the input R7 is configured to the selected Flash Bank.
Page 96 XC82x Boot and Startup Boot and Startup Entry to various boot modes such as User mode, Boot-loader mode (BSL) and On-chip Debug (OCDS) mode are done by the startup firmware in the Boot ROM. The startup firmware will depend on the Boot Mode Index (BMI) value to enter each boot mode.
Page 97 XC82x Boot and Startup For code protection, user may want to erase all flash contents before executing this code. Detailed description of these user routines are found in the Boot ROM User Routines Chapter. Note: A soft reset will be performed after the BMI has been updated. Switching off the supply voltage before the soft reset happened may cause the BMI to be updated wrongly.
Page 98 XC82x Boot and Startup USER_ID, Byte 1 Field Bits Description [15:8] Inverse of Boot Mode Index The inverse of BMI. BMI is checked for validity with BMI. BMI is valid when BMI + BMI + 1 = 0 USER_ID, Byte 2...
Page 99: Boot-Loader Mode
. This includes checking the programmed BMI value to enter the selected Boot ROM operating modes. The memory organization of the XC82x shown in this document is after the Boot ROM address switch where the different operating modes are executed.
Page 100 XC82x Boot and Startup 5.2.4 OCDS Mode If the OCDS mode is selected, the debug mode will be entered for debugging program code. The OCDS hardware is initialized and a jump to program memory address 0000 is performed next. The user code in the Flash memory is executed and the debugging process may be started.
Page 101 UART Boot-Loader UART Boot-Loader The XC82x includes a UART Boot-Loader (BSL) Mode that can be entered with the BMI settings as described in Boot and Startup chapter. The main purpose of BSL Mode is to allow easy and quick programming/erasing of the Flash and XRAM via UART.
Page 102: General Description
XC82x UART Boot-Loader Phase I: Automatic Serial Synchronization to the Host Upon entering UART BSL Mode, a serial connection is established and the transfer speed (baud rate) of the serial communication partner (host) is automatically synchronized in the following steps: •...
Page 103 XC82x UART Boot-Loader 1st negative transition, T2 automatically Last captured value of T2 EOFSYN bit is set, set T2RHEN bit starts upon negative transition T2 is stopped SYN CHAR (55 SYN BREAK Start Stop UART_INIT_ID 0x55 (Dual pins UART) Captured Value (8 bits)
Page 104: Serial Communication Protocol
Acropolis family, the shift operation causes a loss in the decimal digits, thus reducing the baud rate accuracy. Therefore in XC82x, the concept (SFRs BGL and BGH) is implemented in such a way that the actual shift (division) is not necessary by firmware as it will be executed by hardware.
Page 105 XC82x UART Boot-Loader Block Type Data Area Checksum (1 byte) (X bytes) (1 byte) • Block Type: the type of block, which determines how the data in the data area is interpreted. Implemented block types are: – 00 type “HEADER”...
Page 106 In both error cases the UART BSL routine awaits the actual block from the host again. There is no flash protection, thus the flash protection type error is removed for XC82x. UART BSL does not check for validity of address of XRAM/Flash, it is to the user’s responsibility to ensure that the DPTR of Flash/XRAM is valid.
Page 107 XC82x UART Boot-Loader Table 6-4 Possible Responses for Various Block Types Mode Header Block Data Block EOT Block Acknowledge, Block Type Acknowledge, Block Acknowledge, Block Error, Checksum Error Type Error, Checksum Type Error, Error Checksum Error Acknowledge, Block Type Error, Checksum Error...
Page 108 XC82x UART Boot-Loader Table 6-5 Definitions of Responses Response Value Description Block Reasons / Implications Corrective Type Mode Action Acknow- Head 1, 3 The requested operation will ledge be performed once the response is sent. 6, A The requested operation has...
Page 109 XC82x UART Boot-Loader Data Area Block Type Checksum Mode Mode Data (1 byte) (Header Block) (1 byte) (5 bytes) Description: • : The block type, which marks the block as a Header Block • Mode: The working mode. The implemented working modes are: –...
Page 110 XC82x UART Boot-Loader Note: The Block-Length refers to the whole length (block type, data area and checksum) of the following transfer block (Data Block or EOT Block). For each transmission, length of Data Block(s) and EOT Block should be the same.
Page 111 XC82x UART Boot-Loader 6.2.2.3 Mode1: Execute customer code in XRAM Mode 1 is used to execute a customer program in the XRAM of the µC at 0F000 . The Header Block for this working mode has the following structure: The Header Block...
Page 112 XC82x UART Boot-Loader Note: If the data starts in a non-page address, PC Host must fill up the beginning vacancies with 00 and provide the start address of that page address. For e.g., if data starts in 0F82 , the PC Host will fill up the addresses 0F80...
Page 113 XC82x UART Boot-Loader Not used: The length is (Block_Length-3-Last_Codelength) and should be filled with zeros. 6.2.2.5 Mode3: Execute customer code in FLASH Mode 3 is used to execute a customer program in the Flash of the µC at 0000 . The...
Page 114 XC82x UART Boot-Loader 6.2.2.7 Mode6: Program 4 bytes of USER_ID Mode 6 is used to program User indentification, USER_ID (4 bytes). The Header block for this working mode has the following structure: The Header Block Data Area Checksum USER_ID_ USER_ID_...
Page 115 XC82x UART Boot-Loader Option: This byte will determine the 4 bytes data to be sent to the host. Only option 00 - 02 are valid options. - Chip Identification Number (MSB byte 1... LSB byte 4) - USER_ID (MSB byte 1... LSB byte 4) In Mode A, the header block is the only transfer block to be sent by the host.
Page 116: System Control Unit
The XC82x provides a range of utility features for secure system performance under critical conditions (e.g., brownout). At the center of the XC82x clock system is the Clock Control Unit (CCU), which generates a master clock frequency using the 48 MHz oscillator. In-phase synchronized clock signals are derived from the master clock and distributed throughout the system.
Page 117 The EVR works within an input voltage range of 3.0 V to 5.5V under full operation condition and within an input range down to 2.5 V under reduced voltage condition. XC82x will only work in power down mode or in active mode with limited load available in the reduced voltage condition.
Page 118 If the conditions are not met, a brownout reset may be triggered. A guideline of the current consumption for some of the modules is also available in the datasheet. Note: The full operation of XC82x is specified for 3 V < V < 5.5 V. User’s Manual...
Page 119 XC82x System Control Unit 7.1.2 EVR Register Description The SDCON is used to enable or disable the various detectors. The status of V threshold levels are also indicated in this register. The bit field PAGE of SCU_PAGE register must be programmed before accessing these registers.
Page 120: Type Description
XC82x System Control Unit Field Bits Type Description VDDCTH Threshold Indication Below V prewarning threshold level. Above V prewarning threshold level. Note: It is not affected by the bit VDDCPW. VDDPTH Threshold Indication Below V prewarning threshold level. Above V prewarning threshold level.
Page 121: Reset Control
XC82x System Control Unit Reset Control The XC82x has five types of resets: power-on reset, watchdog timer reset, soft reset, power-down wake-up reset, and brownout reset. When the XC82x is first powered up or with brownout condition triggered by supply voltage input(s) going below the threshold, proper voltage thresholds must be reached before the system starts operation with the release of the system reset.
Page 122: Watchdog Timer Reset
7.2.1.4 Power-Down Wake-Up Reset Power is still applied to the XC82x during power-down mode, as the low power voltage regulator is still operating. If power-down mode is entered appropriately, all important system states will have been preserved in the Flash by software.
Page 123: Module Reset Behavior
7.2.2 Module Reset Behavior Table 7-1 lists the functions of the XC82x and the various reset types that affect these functions. The symbol “ ” signifies that the particular function is reset to its default state. Table 7-1 Effect of Reset on Modules/Functions...
Page 124 XC82x System Control Unit 7.2.3 Reset Control Register Description RSTCON register consist of the indication bits of a wake-up event, WDT reset and soft reset. Table 7-2 shows the reset value of RSTCON register after these events. RSTCON Reset Control Register...
Page 125 XC82x System Control Unit Table 7-2 Reset Value of Register RSTCON Reset Source Reset Value Power-down Wake-up Reset 0000 0001 WDT Reset 0000 0010 Soft Reset 0000 0100 Power-On Reset/Brown-out Reset 0000 0000 User’s Manual 7-10 V1.0, 2010-02...
Page 126 System Control Unit Clock System and Control Figure 7-2 shows the block diagram of the clock system in XC82x. It consists of a 48 MHz oscillator and a clock control unit (CCU). The system clock is generated by the 48 MHz internal oscillator. In addition, is also the input clock to the Clock Control Unit (CCU).
Page 127 7.3.1 Oscillator Watchdog There are 2 oscillator watchdogs in XC82x, namely, the 48 MHz oscillator watchdog (48 MHz OWD) and 75 KHz oscillator watchdog(75 KHz OWD). The 48 MHz OWD monitors the 48 MHz clock source. Only incoming frequencies that are below 40 MHz are detected.
Page 128 48 MHz or 75 KHz clock source. The XC82x remains in this loss of clock state until the next power on reset or after a successful clock recovery has been performed. A clock recovery could be carried out by restarting the detection.
Page 129 XC82x System Control Unit 7.3.3 CCU Register Description The registers of the clock control unit are reset to the default value after any type of reset. Register OSC_CON controls the 48 MHz oscillator watchdog and 75 KHz oscillattor watchdog. .
Page 130 XC82x System Control Unit Field Bits Type Description [5:3], Reserved Returns 0 if read; should be written with 0. Note: The reset value of OSC_CON register is 0000 0110 . One clock after reset, bits 48MOSC2L and 75KOSC2L will be set to 0 if both oscillators are running, then the value 0000 0000 will be observed.
Page 131: Power Management
Figure 7-3 Transition between Power Saving Modes (without reset) In XC82x, all functions must be operational in the active mode and idle mode when the normal V supply range of 3.0 V to 5.5 V is applied to the system. For reduced voltage condition in active mode and idle mode, required functions as needed by user will be available as long as the active current is kept under the limits.
Page 132: Functional Description
7.4.1.2 Power Down Mode In order to achieve different levels of power saving, the XC82x has two types of power down modes, Power Down mode 1 and 2. Generally, the 48 MHz oscillator and the Flash memory are put into power down state in all the modes. In addition, the main voltage regulator is switched off, with only low power voltage regulator still operating in these power down modes.
Page 133 XC82x System Control Unit Note: EXICON0.EXINT0 = 11 cannot be used to wake-up from power down mode. Table 7-3 Modules Behavior in Power Down Mode Modules Power Down Mode 1 Power Down Mode 2 75 KHz OSC 75 KHz OWD 1) N indicates that the module is shut down and Y indicates that it can run (if enabled) in power down mode.
Page 134 XC82x System Control Unit of the status of the 75 KHz oscillation is possible. This is because the 75 KHz oscillator watchdog is powered down. To exit power down mode 2, the real-time clock wake up event can be used. Besides this wake-up source, it can also be awakened when it receives an external wake-up signal via EXINT0 pin by setting bit PMCON0.EWS to 1.
Page 135 XC82x System Control Unit 4. The on-chip oscillator is started. Typically, the on-chip oscillator takes approximately 10 us to stabilize. 5. Subsequently, the FLASH will enter ready-to-read mode. This does not require the typical 160 µs as is the case for the normal reset. The timing for this part can be ignored.
Page 136 XC82x System Control Unit 7.4.1.3 Peripheral Clock Management The amount of reduction in power consumption that can be achieved by this feature depends on the number of peripherals running. Peripherals that are not required for a particular functionality can be disabled by gating off the clock inputs. For example, in idle mode, if all timers are stopped, and ADC, CCU6, MDU and the serial interfaces are not running, maximum power reduction can be achieved.
Page 137 XC82x System Control Unit Field Bits Type Description LTS_DIS LEDTSCU Disable Request. Active high. LEDTSCU is in normal operation. Request to disable the LEDTSCU. (default) IIC_DIS IIC Disable Request. Active high. IIC is in normal operation. Request to disable the IIC. (default) Reserved Returns 0 if read;...
Page 138 XC82x System Control Unit 7.4.2 Power Management Register Description PMCON0 Power Mode Control Register 0 Reset Value: 01 RMAP: 0, PAGE: 1 WKSEL PDMODE Field Bits Type Description External interrupt 0 Wake-up Source Selected External interrupt 0 wake-up is not selected.
Page 139 XC82x System Control Unit PCON [Note: This register is located within XC800 core] Power Control Register [Not bitaddressable](87 Reset Value: 00 RMAP: 0, PAGE: X SMOD IDLE Field Bits Type Description IDLE Idle Mode Enable Do not enter Idle Mode Enter Idle Mode User’s Manual...
Page 140 XC82x System Control Unit SCU Register Mapping The system control SFRs are used to control the overall system functionalities, such as interrupts, variable baud rate generation, clock management, bit protection scheme and oscillator. The SFRs are located in the standard memory area (RMAP = 0) and are organized into 8 pages.
Page 141 XC82x System Control Unit Field Bits Type Description [7:6] Operation Manual page mode. The value of STNR is ignored and PAGE is directly written. New page programming with automatic page saving. The value written to the bit positions of PAGE is stored. In parallel, the former contents of PAGE are saved in the storage bit field STx indicated by STNR.
Page 142: Watchdog Timer
The CPU must service the WDT within this interval to prevent the WDT from causing an XC82x system reset. Hence, routine service of the WDT confirms that the system is functioning properly. This ensures that an accidental malfunction of the XC82x will be aborted in a user-specified time period.
Page 143 XC82x Watchdog Timer System Information This section consist of the system information required to use the WDT. 8.2.1 Reset effects The Watchdog Timer maintains a counter which must be refreshed or cleared periodically. Otherwise, the counter will overflow and the watchdog reset will be asserted.
Page 144 XC82x Watchdog Timer Table 8-1 WDT Events’ Non-maskable Interrupt Node Control Event Interrupt Node Interrupt Node Flag Vector Enable Bit Address WDT Overflow NMICON.NMIWDT NMISR.FNMIWDT 8.2.4 Module Suspend Control The timer in WDT is by default suspended on entering debug mode. The WDT can be allowed to run in debug mode by clearing the bit WDTSUSP in SFR MODSUSP to 0.
Page 145 WDT is ignored and the WDT cannot be disabled. A reset (WDTRST) of the XC82x is imminent and can no longer be avoided. The occurrence of a WDT reset is indicated by the bit WDTRST in RSTCON register. If refresh happens at the same time an overflow occurs, WDT will not go into prewarning period The WDT must be serviced periodically so that its count value will not overflow.
Page 146 XC82x Watchdog Timer is generated in this instance. The window boundary is from 0000 to the value obtained from the concatenation of WDTWINB and 00 . This feature can be enabled by WINBEN. After being serviced, the Watchdog Timer continues counting up from the value (<WDTREL>...
Page 147 XC82x Watchdog Timer Table 8-2 Watchdog Time Ranges Reload Value in WDTREL 75 KHz Input frequency 3.4 ms 440 ms 874 ms Note: For safety reasons, the user is advised to rewrite WDTCON each time before the WDT is serviced.
Page 148: Registers Description
XC82x Watchdog Timer Registers Description Five SFRs control the operations of the WDT. They can be accessed from the mapped SFR area. Table 8-3 lists the addresses of these SFRs. Table 8-3 Register Map Address Page Register WDTCON WDTREL WDTWINB...
Page 149 XC82x Watchdog Timer WDTCON Watchdog Timer Control Register Reset Value: 00 RMAP: 0, PAGE: 1 WINBEN WDTPR WDTEN WDTRS Field Bits Type Description WDTRS WDT Refresh Start Active high. Set to start refresh operation on the watchdog timer. Cleared automatically by hardware after it is set by software.
Page 150 XC82x Watchdog Timer WDTL Watchdog Timer, Low Byte Reset Value: 00 RMAP: 0, PAGE: 4 Field Bits Type Description [7:0] Watchdog Timer Current Value WDTH Watchdog Timer, High Byte Reset Value: 00 RMAP: 0, PAGE: 4 Field Bits Type Description...
Page 151 XC82x Watchdog Timer Field Bits Type Description WDTWINB [7:0] Watchdog Window-Boundary Count Value This value is programmable. Within this Window- Boundary range from 0000 to (WDTWINB, 00 the WDT cannot do a Refresh, else it will cause a WDTRST to be asserted.
Page 152: Interrupt System
Interrupt Sources The XC82x supports 14 interrupt vectors with four priority levels. Ten of these interrupt vectors are assigned to the on-chip peripherals: Timer 0, Timer 1, UART and SSC are each assigned one dedicated interrupt vector; while Timer 2, A/D Converter, LIN, LEDTSCU and the Capture/Compare Unit share six interrupt vectors.
Page 153 XC82x Interrupt System Highest Timer 0 Lowest Overflow Priority Level TCON.5 000B IP.1/ IPH.1 IEN0.1 Timer 1 Overflow TCON.7 001B IP.3/ IEN0.3 IPH.3 UART Receive SCON.0 >=1 UART 0023 Transmit IP.4/ IEN0.4 SCON.1 IPH.4 EINT0 TCON.1 0003 IP.0/ IEN0.0 IPH.0 TCON.0...
Page 154 XC82x Interrupt System Highest Timer 2 Overflow T2_T2CON.7 Lowest TF2EN Priority Level >=1 T2_T2CON1.1 T2EX EXF2 T2_T2CON.6 EXEN2 EXF2EN T2_T2CON1.0 T2_T2CON.3 EDGES >=1 T2_T2MOD.5 002B IP.5/ IEN0.5 IPH.5 End of EOFSYN Synch Byte >=1 LINST.4 ERRSYN Synch Byte SYNEN LINST.5 Error LINST.6...
Page 155 XC82x Interrupt System Highest SSC_EIR Lowest EIREN IRCON1.0 Priority Level MODIEN.0 SSC_TIR >=1 IRCON1.1 TIREN MODIEN.1 003B ESSC IP1.1/ SSC_RIR IEN1.1 IPH1.1 IRCON1.2 RIREN MODIEN.2 EXINT2 EINT2 IRCON0.2 EXINT2 EXICON0.4/5 MDU_0 IRDY 0043 >=1 MDUSTAT.0 IP1.2/ IEN1.2 MDUCON.7 IPH1.2 MDU_1 IERR MDUSTAT.1...
Page 156 XC82x Interrupt System Highest Lowest Priority Level EXINT3 EINT3 IRCON0.3 EXINT3 EXICON0.6/7 EXINT4 EINT4 IRCON0.4 EXINT3 EXICON1.0/1 EXINT5 EINT5 IRCON0.5 >=1 EXINT5 EXICON1.2/3 004B IP1.3/ IEN1.3 IPH1.3 EXINT6 EINT6 IRCON0.6 EXINT6 EXICON1.4/5 CFRTC Compare/ Wakeup ECRTC RTCON.6 >=1 RTCON.4 SFRTC SEC_TIME RTCON.7...
Page 157 XC82x Interrupt System Highest Lowest Priority Level CCU6 Node 0 CCU6SR0 0053 IRCON2.0 ECCIP0 IP1.4/ IEN1.4 IPH1.4 CCU6SR1 CCU6 Node 1 IRCON2.4 >=1 005B ECCIP1 LED/TS IP1.5/ Time-frame IEN1.5 IPH1.5 GLOBCTL1.5 ITF_EN GLOBCTL1.4 CCU6SR2 CCU6 Node 2 CCU6 0063 IRCON3.0...
Page 158 XC82x Interrupt System WDT Overflow FNMIWDT NMISR.0 NMIWDT NMICON.0 48MHz or 75KHz FNMIOSCCLK Loss-of-clock NMISR.1 NMIOSCCLK NMICON.1 FNMIFLASH Flash NMIFLASH NMISR.2 NMICON.2 IRAM read FNMIRR event* MMICR.2 NMIRRE >=1 MMICR.0 FNMIOCDS >=1 NMISR.3 NMIOCDS IRAM write FNMIRW event* NMICON.3 MMICR.3 NMIRWE MMICR.1...
Page 159 This vector is accessed to service the corresponding interrupt node request. The interrupt service of each interrupt node can be individually enabled or disabled via an enable bit. The assignment of the XC82x interrupt sources to the interrupt vector address and the corresponding interrupt node enable bits are...
Page 160 XC82x Interrupt System Table 9-1 Interrupt Vector Address (cont’d) Interrupt Vector Assignment for XC82x Enable Bit Node Address XINTR6 0033 EADC IEN1 XINTR7 003B ESSC XINTR8 0043 External Interrupt 2 XINTR9 004B External Interrupt 3 External Interrupt 4 External Interrupt 5...
Page 161: Interrupt Structure
NMI events). No interrupt will be requested for any occurred event that has its interrupt enable bit disabled. The XC82x has, in general, two interrupt structures distinguished mainly by the manner in which the pending interrupt request (one per interrupt vector/node going directly to the core) is generated (due to the events) and cleared.
Page 162 Figure 9-7 Interrupt Structure 1 For the XC82x, interrupt sources Timer 0, Timer 1, external interrupt 0 and external interrupt 1 (each have a dedicated interrupt node) will have their respective interrupt status flags TF0, TF1, IE0 and IE1 in register TCON cleared by the core once their corresponding pending interrupt request is serviced.
Page 163: Interrupt Handling
XC82x Interrupt System All qualified flags of the interrupt node Corresponding interrupt event status acknowledge flag (from core) pending Event interrupt request interrupt clear request set/clear Event occurrence interrupt node Corresponding enable bit event interrupt to core enable bit * Implemented as latch, cannot set by software...
Page 164: Interrupt Response Time
XC82x Interrupt System and the interrupt system will generate a LCALL to the node’s service routine, provided this hardware-generated LCALL is not blocked by any of the following conditions: 1. An interrupt of equal or higher priority is already in progress.
Page 165 XC82x Interrupt System are right for it to be acknowledged, a hardware subroutine call to the requested service routine will be the next instruction to be executed. The call itself takes two machine cycles. Thus, a minimum of three complete machine cycles will elapse from activation of...
Page 166 XC82x Interrupt System CCLK 4-cycle current instruction Interrupt (MUL or DIV) request sampled active Interrupt instruction at request LCALL Interrupt interrupt vector polled request (last cycle of sampled current instruction) Interrupt response time = 6 x machine cycle Figure 9-10 Interrupt Response Time for Condition 2...
Page 167: Registers Description
XC82x Interrupt System Registers Description Interrupt Special Function Registers or bits are used for interrupt configuration such as node enable, external interrupt control, interrupt flags and interrupt priority setting. Table 9-3 lists the SFRs and corresponding address. Table 9-3 Register Map...
Page 168 XC82x Interrupt System 9.5.1 Interrupt Node Enable Registers Each interrupt node can be individually enabled or disabled by setting or clearing the corresponding bit in the interrupt enable registers IEN0 and IEN1. Register IEN0 also contains the global interrupt masking bit (EA), which can be cleared to block all pending interrupt requests at once.
Page 169 XC82x Interrupt System Field Bits Type Description Global Interrupt Mask All pending interrupt requests (except NMI) are blocked from the core. Pending interrupt requests are not blocked from the core. Reserved Returns 0 if read; should be written with 0.
Page 170 XC82x Interrupt System Field Bits Type Description ECCIP2 Interrupt Node XINTR12 Enable XINTR12 is disabled XINTR12 is enabled ECCIP3 Interrupt Node XINTR13 Enable XINTR13 is disabled XINTR13 is enabled The bit field PAGE of SCU_PAGE register must be programmed before accessing the NMICON register.
Page 171: External Interrupt Control Registers
9.5.2 External Interrupt Control Registers The seven external interrupts, EXT_INT[6:0], are driven into the XC82x from the ports. External interrupts can be positive, negative or double edge triggered. Registers EXICON0 and EXICON1 specify the active edge for the external interrupt. Among the external interrupts, external interrupt 0 and external interrupt 1 can be selected to bypass edge detection in the SCU, for direct feed-through to the core.
Page 172 XC82x Interrupt System EXICON0 External Interrupt Control Register 0 (EF Reset Value: F0 RMAP: 0, PAGE: 0 EXINT3 EXINT2 EXINT1 EXINT0 Field Bits Type Description EXINT0 External Interrupt 0 Trigger Select Interrupt on falling edge. Interrupt on rising edge. Interrupt on both rising and falling edge.
Page 173 XC82x Interrupt System EXICON1 External Interrupt Control Register 1 (F4 Reset Value: 3F RMAP: 0, PAGE: 0 EXINT6 EXINT5 EXINT4 Field Bits Type Description EXINT4 External Interrupt 4 Trigger Select Interrupt on falling edge. Interrupt on rising edge. Interrupt on both rising and falling edge.
Page 174: Type Description
XC82x Interrupt System Field Bits Type Description EXINT0IS [4:3] External Interrupt 0 Input Selection External Interrupt Input EXINT0_0 is selected. External Interrupt Input EXINT0_1 is selected. External Interrupt Input EXINT0_2 is selected. External Interrupt Input EXINT0_3 is selected. EXINT1IS External Interrupt 1 Input Select External Interrupt Input EXINT1_0 is selected.
Page 175 XC82x Interrupt System time, hardware will have higher priority. The bit field PAGE of SCU_PAGE register must be programmed before accessing IRCONx and NMISR register. IRCON0 Interrupt Request Register 0 Reset Value: 00 RMAP: 0, PAGE: 0 EXINT6 EXINT5 EXINT4...
Page 176 XC82x Interrupt System Field Bits Type Description Transmit Interrupt Flag for SSC This bit is set by hardware and can only be cleared by software. Interrupt event has not occurred. Interrupt event has occurred. Receive Interrupt Flag for SSC This bit is set by hardware and can only be cleared by software.
Page 177 XC82x Interrupt System Field Bits Type Description CCU6SR1 Interrupt Flag 1 for CCU6 This bit is set by hardware and can only be cleared by software. Interrupt event has not occurred. Interrupt event has occurred. [3:1], Reserved [7:5] Returns 0 if read; should be written with 0.
Page 178 XC82x Interrupt System TCON Timer and Counter Control/Status Register(88 Reset Value: 00 RMAP: X, PAGE: X Field Bits Type Description External Interrupt 0 Flag Set by hardware when external interrupt 0 event is detected. Cleared by hardware when the processor vectors to interrupt routine.
Page 179 XC82x Interrupt System Field Bits Type Description Serial Interface Receiver Interrupt Flag Set by hardware if a serial data byte has been received. Must be cleared by software. Serial Interface Transmitter Interrupt Flag Set by hardware at the end of a serial data transmission.
Page 180 XC82x Interrupt System Field Bits Type Description FNMIVDDP VDDP Prewarning NMI Flag No V NMI has occurred. prewarning (drop below 4.0V for external power supply of 5.0V) has occurred. FNMIECC ECC NMI Flag No ECC error has occurred. ECC error has occurred.
Page 181: Interrupt Priority Registers
XC82x Interrupt System 9.5.4 Interrupt Priority Registers Each interrupt node can be individually programmed to one of the four priority levels available. Two pairs of Interrupt Priority Registers are available to program the priority level of the each interrupt vector. The first pair of Interrupt Priority Registers are SFRs IP and IPH.
Page 182 XC82x Interrupt System Interrupt Priority High Register Reset Value: 00 RMAP: X, PAGE: X PT2H PT1H PX1H PT0H PX0H Field Bits Type Description PX0H Priority Level High Bit for Interrupt Node XINTR0 PT0H Priority Level High Bit for Interrupt Node XINTR1...
Page 183 XC82x Interrupt System Field Bits Type Description PCCIP2 Priority Level Low Bit for Interrupt Node XINTR12 PCCIP3 Priority Level Low Bit for Interrupt Node XINTR13 IPH1 Interrupt Priority 1 High Register Reset Value: 04 RMAP: X, PAGE: X PCCIP3H PCCIP2H...
Page 184 XC82x Interrupt System Table 9-5 Location of the Interrupt Flags (cont’d) Interrupt Event Interrupt Flag Timer2 Overflow T2_T2CON Timer2 External Event EXF2 T2_T2CON UART Receive SCON UART Transmit SCON LIN End of Synch Byte EOFSYN LINST LIN Synch Byte Error...
Page 185 XC82x Interrupt System Table 9-5 Location of the Interrupt Flags (cont’d) Interrupt Event Interrupt Flag 48 MHz and 75 KHz Oscillator NMI FNMIOSCCLK NMISR 32.768 KHz XTAL Oscillator NMI FNMIXTALCLK NMISR Flash Operation Complete NMI FNMIFLASH NMISR OCDS NMI FNMIOCDS...
Page 186: Debug System
XC82x Debug System Debug System This chapter describes the XC800 debug system, in particular focus on the OCDS unit which provides the hardware to support debug functionality. 10.1 Overview The debug system comprises of the On-Chip Debug Support (OCDS) unit and Debug- Monitor in ROM which provides basic debug functionality for XC800-based systems, controlled directly by an external tool via debug interface pin(s).
Page 187: Product Specific Information
10.2 Product Specific Information This section provides product specific information relevant to the OCDS. 10.2.1 Pinning Figure 10-1 describes the debug pin function in XC82x. Table 10-1 XC82x Pin Functions and Selection Function Desciption Selected By P0.6 SPD_0 Single-pin debug access port: Selectable via BMI value.
Page 188 XC82x Debug System Table 10-3 OCDS Events’ Interrupt Node Control Event Interrupt Node Interrupt Node Flag Vector Enable Bit Address IRAM read event NMICON.NMIOCDS NMISR.FNMIOCDS 73 IRAM write event 10.2.4 Debug Suspend Control It is enabled for selected modules to suspend operation when Monitor Mode becomes active.
Page 189 LED and Touch-sense Counters will be suspended. [7:6] Reserved Returns 0 if read; should be written with 0. 10.2.5 JTAG ID The JTAG ID for the XC82x devices is given in Table 10-4. Table 10-4 JTAG ID Number Device Type Device Name...
Page 190 XC82x Debug System 10.3 Functional Overview of the Debug System XC800 debug-operation is based on close interaction between the OCDS-hardware and the Monitor program in ROM. These operations are elaborated in the following. 10.3.1 Recognizing Debug-events The OCDS hardware takes care to startup properly the Monitor, in case some Debug- event happens.
Page 191 XC82x Debug System Software Breakpoints These are implemented by storing into the code XC800-specific TRAP instruction (not 8051-standard), while at the same time TRAP_EN bit within the Extended Operation (EO) register is also set to 1. Upon fetching a TRAP instruction, a breakpoint is generated and the relevant Break Action is taken.
Page 192 XC82x Debug System 10.3.3 Debug Suspend Control Next to the basic debug functionality - setting breakpoints and halting the execution of user software - OCDS supports also for module suspend during debugging. As long as the device is in monitor mode (i.e. while the user software is not running but in break) and if debug suspend functionality is generally enabled by on-chip software, modules or functions can be suspended in this duration.
Page 193 • Break Now The events of this type are asynchronous to the code execution inside the XC82x and there is no “instruction causing the debug event” in this case. The debug action is performed by OCDS “as soon as possible” once the debug event is raised.
Page 194 XC82x Debug System • CMP1 A 16-bit comparator between the two HWBP1 registers (A-side) and the 16-bit Program Memory Address Bus (B-side). Two output signals are generated: – A=B - (break on IP= HWBP1 ) – A>=B when activated together with A=<B from CMP0 - (break on HWBP0 =<IP<= HWBP1) •...
Page 195 XC82x Debug System • CMPWL3, CMPWH3 Two 8-bit comparators: – CMPWL3 - between HWBP3L register (A-side) and the 8-bit IRAM Destination Address Bus (B-side), generating A=<B; – CMPWH3 - between HWBP3H register (A-side) and the 8-bit IRAM Destination Address Bus (B-side), generating A>=B.Then: break on HWBP3L=<IRAM Write Address<=HWBP3H.
Page 196 XC82x Debug System Upon matching a not enabled Software Breakpoint, the user software execution is suppressed for 4 clock cycles after the TRAP instruction. 10.5 Reactions on Breakpoints without Monitor Entry In case a Break-event happens while Monitor Mode is disabled , the Monitor program is not started (MM_no_entry) but another action is triggered by OCDS system.
Page 197 XC82x Debug System 10.6 NMI Request and Control by OCDS The OCDS module provides hardware allowing to generate a NMI request itself as well as to control the general NMI-processing within the XC800 system. 10.6.1 NMI request from OCDS The OCDS generates one interrupt request at the output ocds_nmi_o. This signal goes to the Interrupt-Management Module into XC800 SCU (System Control Unit), where it sets a flag within NMI Status Register NMISR.
Page 198: Registers Description
XC82x Debug System a) can identify OCDS as NMI-requesting source and the type of IRAM-access causing the request by evaluating NMISR.FNMIOCDS (in SCU) and MMICR.FNMIRR/FNMIRW (in OCDS) b) must clear FNMIRR/FNMIRW flags before its end, to allow a proper reaction on next NMIs.
Page 199 XC82x Debug System Table 10-5 Register Map (Direct Addressable) Address Register MMICR HWBPSR HWBPDR MMWR2 Additionally, there are Hardware Breakpoint Registers, which are indirect accessible via HWBPSR (register select) and HWBPDR (data) - refer to Table 10-6 Table 10-7 (for more information look at Section 10.8).
Page 200 XC82x Debug System 10.8.1 Control and Status Registers MMICR Monitor Mode Interrupt Control Register (F4 Reset value: 00 RMAP: 1, PAGE: X FNMIRW FNMIRR NMIRWE NMIRRE Field Bits Type Description NMIRRE NMI upon IRAM read (refer to Section 10.6.1): Disabled...
Page 201 XC82x Debug System 10.8.2 Hardware Breakpoint Registers All of the Hardware Breakpoint Registers HWBP0L..HWBP3H within OCDS can be set to the desired compare-values indirectly - by writing only to one software-accessible register HWBPDR, after BPSEL bitfield within the select-register HWBPSR has been...
Page 202 XC82x Debug System HWBP0L Hardware Breakpoint 0 Low Register written via HWBPDR Reset value: 00 HWBP0L Field Bits Type Description HWBP0L [7:0] The Low Byte from Compare Address HWBP0 HWBP0H Hardware Breakpoint 0 High Register written via HWBPDR Reset value: 00...
Page 203 XC82x Debug System HWBP1H Hardware Breakpoint 1 High Register written via HWBPDR Reset value: 00 HWBP1H Field Bits Type Description HWBP1H [7:0] The High Byte from Compare Address HWBP1 HWBP2L Hardware Breakpoint 2 Low Register written via HWBPDR Reset value: 00...
Page 204 XC82x Debug System HWBP3L Hardware Breakpoint 3 Low Register written via HWBPDR Reset value: 00 HWBP3L Field Bits Type Description HWBP3L [7:0] The Low Byte from Compare Address HWBP3 HWBP3H Hardware Breakpoint 3 High Register written via HWBPDR Reset value: 00...
Page 205 XC82x Debug System Field Bits Type Description MMWR2 [7:0] Work location 2 for the Monitor Program User’s Manual 10-20 V1.0, 2010-02 OCDS, V 2.7.1...
Page 206: Parallel Ports
General Port Operation Description Figure 11-1 shows the block diagram of an XC82x bidirectional port pin. Each port pin is equipped with a number of control and data bits, thus enabling very flexible usage of the pin. By defining the contents of the control register, each individual pin can be configured as an input or an output.
Page 207 XC82x Parallel Ports is switched by software to the data register Px_DATAOUT. Software can set or clear the bit in Px_DATAOUT and therefore directly influence the state of the port pin. If an on- chip peripheral uses the pin for output signals, alternate output lines (AltDataOut) can be switched via the multiplexer to the output driver circuitry.
Page 208 XC82x Parallel Ports Internal PUDSEL Pull -up/Pull -down Select Register Pull-up/Pull-down Control Logic PUDEN Pull -up/Pull -down Enable Register Open Drain Control Register ALTSEL0 Alternate Select Register 0 ALTSEL1 Alternate Select Register 1 ALTSEL2 Pull Alternate Select Device Register 2...
Page 209 XC82x Parallel Ports Figure 11-2 shows the structure of an input-only port pin. Each P2 pin can only function in input mode. Register P2_EN is provided to enable or disable the input driver. When the input driver is enabled, the actual voltage level present at the port pin is translated into a logic 0 or 1 via a Schmitt-Trigger device and can be read via the register P2_DATAIN.
Page 210: Register Map
Parallel Ports 11.1.1 General Register Description This section describes the SFR registers available on the XC82x module. 11.1.1.1 Register Map The Port SFRs are located in the standard memory area (RMAP = 0) and are organized into 4 pages. The PORT_PAGE register is located at address 8E .
Page 211: Register Overview
XC82x Parallel Ports Field Bits Type Description STNR [5:4] Storage Number This number indicates which storage bit field is the target of the operation defined by bit OP. If OP = 10 the contents of PAGE are saved in STx before being overwritten with the new value.
Page 212 XC82x Parallel Ports Table 11-2 Port Registers Register Short Name Register Long Name Description Px_DATAOUT Port x Data Out Register Page 11-7 Px_DATAIN Port x Data In Register Page 11-8 Px_OD Port x Open Drain Control Register Page 11-8 Px_PUDSEL...
Page 213: Type Description
XC82x Parallel Ports Port Data In Register If a port pin is used as general purpose input, the value at a port pin can be read through the register Px_DATAIN. The data register Px_DATAIN always contains a latched value of the assigned port pin, even if the port pin is assigned as output.
Page 214 XC82x Parallel Ports Pull-Up/Pull-Down Device Register Internal pull-up/pull-down devices can be optionally applied to a port pin. This offers the possibility to configure the following input characteristics: • Tristate • High-impedance with a weak pull-up device • High-impedance with a weak pull-down device and the following output characteristics: •...
Page 215 XC82x Parallel Ports Field Bits Type Description Pull-Up/Pull-Down Enable at Port x Bit n (n = 0 - 7) Pull-up or Pull-down device is disabled Pull-up or Pull-down device is enabled Alternate Input Functions The number of alternate functions that uses a pin for input is not limited. Each port control logic of an I/O pin provides several input paths of digital input value via register.
Page 216 XC82x Parallel Ports Field Bits Type Description Pin Output Functions (n = 0 - 7) Configuration of Px_ALTSEL0.Pn, Px_ALTSEL1.Pn and Px_ALTSEL2.Pn for GPIO or alternate settings: 000 Normal GPIO 001 Alternate Select 1 010 Alternate Select 2 011 Alternate Select 3...
Page 217 XC82x Parallel Ports 11.2 Port 0 Port 0 is a 7-bit general purpose bidirectional port. It uses the standard bidirectional pad for each pin. The registers of Port 0 are summarized in Table 11-3. Table 11-3 Port 0 Registers Register Short Name Register Long Name...
Page 218 XC82x Parallel Ports Table 11-4 Port 0 Input/Output Functions (cont’d) Port Pin Input/Output Select Connected Signal(s) From/to Module P0.1 Input P0_DATAIN.P1 ALT1 T0_0 Timer 0 ALT2 CC61_1 CCU6 ALT3 MTSR_3 ALT4 MRST_2 ALT5 T13HR_0 CCU6 ALT6 CCPOS1_0 CCU6 ALT7 TSIN1...
Page 219 XC82x Parallel Ports Table 11-4 Port 0 Input/Output Functions (cont’d) Port Pin Input/Output Select Connected Signal(s) From/to Module P0.3 Input P0_DATAIN.P3 ALT1 – ALT2 CC60_1 CCU6 ALT3 SDA_1 ALT4 – ALT5 – ALT6 CTRAP#_0 CCU6 ALT7 TSIN3 LEDTSCU Output P0_DATAOUT.P3...
Page 220 XC82x Parallel Ports Table 11-4 Port 0 Input/Output Functions (cont’d) Port Pin Input/Output Select Connected Signal(s) From/to Module P0.5 Input P0_DATAIN.P5 ALT1 RXD_0 UART ALT2 RTCCLK ALT3 MTSR_0 ALT4 MRST_1 ALT5 EXINT0_0 ALT6 – ALT7 TSIN5 LEDTSCU Output P0_DATAOUT.P5 ALT1...
Page 221 XC82x Parallel Ports Table 11-4 Port 0 Input/Output Functions (cont’d) Port Pin Input/Output Select Connected Signal(s) From/to Module P0.6 Input P0_DATAIN.P6 ALT1 RXD_1 UART ALT2 SDA_0 ALT3 MTSR_1 ALT4 MRST_0 ALT5 EXINT0_1 ALT6 T2EX_0 Timer 2 ALT7 TSIN6 LEDTSCU OTHERS...
Page 222: Registers Description
XC82x Parallel Ports 11.2.2 Registers Description P0_DATAIN Port 0 Data In Register Reset Value: XX RMAP: 0, PAGE: 0 Field Bits Type Description Port 0 Pin n Data Value (n = 0 - 6) Port 0 pin n data value = 0...
Page 223 XC82x Parallel Ports P0_OD Port 0 Open Drain Control Register Reset Value: 7F RMAP: 0, PAGE: 3 Field Bits Type Description Port 0 Pin n Open Drain Mode (n = 0 - 6) Normal Mode, output is actively driven for 0 and...
Page 224 XC82x Parallel Ports P0_PUDEN Port 0 Pull-Up/Pull-Down Enable Register(86 Reset Value: 50 RMAP: 0, PAGE: 1 Field Bits Type Description Pull-Up/Pull-Down Enable at Port 0 Bit n (n = 0 - 6) Pull-up or Pull-down device is disabled Pull-up or Pull-down device is enabled Reserved Returns 0 if read;...
Page 225 XC82x Parallel Ports P0_ALTSEL1 Port 0 Alternate Select Register 1 Reset Value: 00 RMAP: 0, PAGE: 2 Field Bits Type Description Table 11-5 (n = 0 - 6) Reserved Returns 0 if read; should be written with 0. P0_ALTSEL2 Port 0 Alternate Select Register 2...
Page 226 XC82x Parallel Ports Table 11-5 Function of Bits P0_ALTSEL2.Pn, P0_ALTSEL1.Pn (cont’d)and P0_ALTSEL0.Pn P0_ALTSEL2.Pn P0_ALTSEL1.Pn P0_ALTSEL0.Pn Function Alternate Select 3 Alternate Select 4 Alternate Select 5 Alternate Select 6 Alternate Select 7 User’s Manual 11-21 V1.0, 2010-02...
Page 227 XC82x Parallel Ports 11.3 Port 1 Port 1 is a general purpose bidirectional port. In XC82x, P1 uses the standard bidirectional pad for each pin. The registers of Port 1 are summarized in Table 11-6. Table 11-6 Port 1 Registers...
Page 228 XC82x Parallel Ports 11.3.1 Functions Port 1 input and output functions are shown in Table 11-7. Table 11-7 Port 1 Input / Output Functions Port Pin Input/Output Select Connected Signal(s) From/to Module P1.0 Input P1_DATAIN.P0 ALT 1 RXD_2 UART ALT 2...
Page 229 XC82x Parallel Ports Table 11-7 Port 1 Input / Output Functions (cont’d) Port Pin Input/Output Select Connected Signal(s) From/to Module P1.2 Input P1_DATAIN.P2 ALT 1 – ALT 2 – ALT 3 – ALT 4 – ALT 5 EXINT4 ALT 6 –...
Page 230 XC82x Parallel Ports Table 11-7 Port 1 Input / Output Functions (cont’d) Port Pin Input/Output Select Connected Signal(s) From/to Module P1.4 Input P1_DATAIN.P4 ALT 1 – ALT 2 – ALT 3 – ALT 4 – ALT 5 EXINT5 ALT 6 –...
Page 231 XC82x Parallel Ports 11.3.2 Registers Description P1_DATAIN Port 1 Data In Register Reset Value: XX RMAP: 0, PAGE: 0 Field Bits Type Description Port 1 Pin n Data Value (n = 0 - 5) Port 1 pin n data value = 0...
Page 232 XC82x Parallel Ports P1_OD Port 1 Open Drain Control Register Reset Value: 3F RMAP: 0, PAGE: 3 Field Bits Type Description Port 1 Pin n Open Drain Mode (n = 0 - 5) Normal Mode, output is actively driven for 0 and...
Page 233 XC82x Parallel Ports P1_PUDEN Port 1 Pull-Up/Pull-Down Enable Register(91 Reset Value: 00 RMAP: 0, PAGE: 1 Field Bits Type Description Pull-Up/Pull-Down Enable at Port 1 Bit n (n = 0 - 5) Pull-up or Pull-down device is disabled (default) Pull-up or Pull-down device is enabled...
Page 234 XC82x Parallel Ports Table 11-8 Function of Bits P1_ALTSEL0.Pn and P1_ALTSEL1.Pn (cont’d) P1_ALTSEL1.Pn P1_ALTSEL0.Pn Function Alternate Select 2 Alternate Select 3 User’s Manual 11-29 V1.0, 2010-02...
Page 235 XC82x Parallel Ports 11.4 Port 2 Port 2 is a general purpose input-only port. In XC82x, Port 2 has 4 pins, P2.0 - P2.3. The registers of Port 2 are summarized in Table 11-9. Table 11-9 Port 2 Registers Register Short Name Register Long Name...
Page 236 XC82x Parallel Ports 11.4.1 Functions Port 2 input and output functions are shown in Table 11-10. Table 11-10 Port 2 Input Functions Port Pin Input/Output Select Connected Signal(s) From/to Module P2.0 Input P2_DATAIN.P0 ALT 1 CCPOS0_1 CCU6 ALT 2 T12HR_2...
Page 237 XC82x Parallel Ports Table 11-10 Port 2 Input Functions (cont’d) Port Pin Input/Output Select Connected Signal(s) From/to Module P2.3 Input P2_DATAIN.P3 ALT 1 CCPOS0_2 CCU6 ALT 2 CTRAP#_2 CCU6 ALT 3 – ALT 4 – ALT 5 T2_2 Timer 2...
Page 238 XC82x Parallel Ports 11.4.2 Registers Description P2_DATAIN Port 2 Data Register Reset Value: 0X RMAP: 0, PAGE: 0 Field Bits Type Description Port 2 Pin n Data Value (n = 0 - 3) Port 2 pin n data value = 0...
Page 239 XC82x Parallel Ports P2_PUDSEL Port 2 Pull-Up/Pull-Down Select Register(93 Reset Value: 0F RMAP: 0, PAGE: 1 Field Bits Type Description Pull-Up/Pull-Down Select Port 2 Bit n (n = 0 - 3) Pull-down device is selected Pull-up device is selected (default)
Page 240 The Multiplication/Division Unit (MDU) provides fast 16-bit multiplication, 16-bit and 32-bit division as well as shift and normalize features. It has been integrated to support the XC82x Core in real-time control applications, which require fast mathematical computations. The MDU uses a total of 14 registers; 12 registers for data manipulation, one register to control the operation of MDU and one register for storing the status flags.
Page 241: System Information
XC82x Multiplication/Division Unit Table 12-1 specifies the number of clock cycles used for calculation in various operations. Table 12-1 MDU Operation Characteristics Operation Result Reminder No. of Clock Cycles Used for Calculation Signed 32-bit/16-bit 32-bit 16-bit Signed 32-bit/16-bit with 32-bit...
Page 242 XC82x Multiplication/Division Unit PMCON1 Peripheral Management Control Register 1(EF Reset Value: DF RMAP: 0, PAGE: 1 IIC_DIS LTS_DIS MDU_DIS T2_DIS CCU_DIS SSC_DIS ADC_DIS Field Bits Type Description MDU_DIS MDU Disable Request. Active high. MDU is in normal operation. Request to disable the MDU. (default) Reserved Returns 0 if read;...
Page 243 XC82x Multiplication/Division Unit Phase One: Load MDx Registers In this phase, the operands are loaded into the MDU Operand (MDx) registers by the CPU. The type of calculation the MDU must perform is selected by writing a 4-bit opcode that represents the required operation into the bit field MDUCON.OPCODE.
Page 244 XC82x Multiplication/Division Unit If q = D div d and r = D mod d then D = q * d + r and | r | < | d | where “D” is the dividend, “d” is the divisor, “q” is the quotient and “r” is the remainder.
Page 245: Error Detection
XC82x Multiplication/Division Unit single left shift on this product gives a Q31 value and the product in Q15 format can be obtained by taking only the upper 16-bit of the 32-bit value. 12.3.5 Division with Single Right Shift The division with single right shift is similar to a signed 32-bit by 16-bit division except that the MDU performs a single right shift first before the division.
Page 246: Interrupt Generation
XC82x Multiplication/Division Unit 12.4 Interrupt Generation The interrupt structure of the MDU is shown in Figure 12-2. There are two possible interrupt events in the MDU, and each event sets one of the two interrupt flags. The interrupt flags is reset by software by writing 0 to it.
Page 247 XC82x Multiplication/Division Unit 12.5 Registers Description The MDU Special Function Registers are accessed from the standard (non-mapped) SFR area. Table 12-4 lists the MDU registers with their addresses. Table 12-4 Register Map Address Name MDU_MDUCON MDU Control Register MDU_MDUSTAT MDU Status Register...
Page 248 XC82x Multiplication/Division Unit Table 12-5 MDx Registers (cont’d) Register Roles of Registers in Operations 16-bit 32/16-bit 16/16-bit Normalize and Multiplication Division Division Shift – D’endH – OperandH M’orL D’orL D’orL Control M’orH D’orH D’orH – Table 12-6 MRx Registers Register...
Page 249 XC82x Multiplication/Division Unit 12.5.1 Operand and Result Registers The MDx and MRx registers are used to store the operands and results of a calculation. MD4 and MR4 are also used as input and output control registers for shift and normalize operations.
Page 250 XC82x Multiplication/Division Unit MDU_MD4 Shift Input Control Register Reset Value: 00 RMAP: 0, PAGE: X SCTR Field Bits Type Description SCTR [4:0] Shift Counter The count written to SCTR determines the number of shifts to be performed during a shift operation.
Page 251: Control Register
XC82x Multiplication/Division Unit 12.5.2 Control Register Register MDUCON contains control bits that select and start the type of operation to be performed. MDU_MDUCON MDU Control Register Reset Value: 00 RMAP: 0, PAGE: X RSEL START OPCODE Field Bits Type Description...
Page 252 XC82x Multiplication/Division Unit Field Bits Type Description Interrupt Routing The two interrupt sources have their own dedicated interrupt lines. The two interrupt sources share one interrupt line INT_O0. Interrupt Enable The interrupt is disabled. The interrupt is enabled. Note: Write access to MDUCON is not allowed when the busy flag MDUSTAT.BSY is set during the calculation phase.
Page 253: Status Register
XC82x Multiplication/Division Unit 12.5.3 Status Register Register MDUSTAT contains the status flags of the MDU. MDU_MDUSTAT MDU Status Register Reset Value: 00 RMAP: 0, PAGE: X IERR IRDY Field Bits Type Description IRDY Interrupt on Result Ready The bit IRDY is set by hardware and reset by software.
Page 254: System Information
XC82x is shown in Table 13-1. This selection is performed by the SFR bits MODPISEL2.T0IS and MODPISEL2.T1IS. Table 13-1 Timer 0 and 1 Pin Functions in XC82x Function Desciption Selected By P0.1 T0_0 Timer 0 Input MODPISEL2.T0IS = 0 P2.1 T0_1...
Page 255: Clocking Configuration
XC82x Timer 0 and Timer 1 The bit field PAGE of SCU_PAGE register must be programmed before accessing the MODPISEL2 register. MODPISEL2 Peripheral Input Select Register 2 Reset Value: 00 RMAP: 0, PAGE: 3 T0IS T1IS T2IS T2EXIS Field Bits...
Page 256 XC82x Timer 0 and Timer 1 13.3 Basic Timer Operations The operations of the two timers are controlled using the Special Function Registers (SFRs) TCON and TMOD. To enable a timer, i.e., allow the timer to run, its control bit TCON.TRx is set.
Page 257: Timer Modes
XC82x Timer 0 and Timer 1 13.4 Timer Modes Timers 0 and 1 are fully compatible and can be configured in four different operating modes, as shown in Table 13-3. The bit field TxM in register TMOD selects the operating mode to be used for each timer.
Page 258 XC82x Timer 0 and Timer 1 13.4.1 Mode 0 Putting either Timer 0 or Timer 1 into mode 0 configures it as an 8-bit timer/counter with a divide-by-32 prescaler. Figure 13-1 shows the mode 0 operation. In this mode, the timer register is configured as a 13-bit register. As the count rolls over from all 1s to all 0s, it sets the timer overflow flag TFx.
Page 259 XC82x Timer 0 and Timer 1 13.4.2 Mode 1 Mode 1 operation is similar to that of mode 0, except that the timer register runs with all 16 bits. Mode 1 operation for Timer 0 is shown in Figure 13-2.
Page 260 XC82x Timer 0 and Timer 1 13.4.3 Mode 2 In Mode 2 operation, the timer is configured as an 8-bit counter (TLx) with automatic reload, as shown in Figure 13-3 for Timer 0. An overflow from TLx not only sets TFx, but also reloads TLx with the contents of THx that has been preset by software.
Page 261 XC82x Timer 0 and Timer 1 13.4.4 Mode 3 In mode 3, Timer 0 and Timer 1 behave differently. Timer 0 in mode 3 establishes TL0 and TH0 as two separate counters. Timer 1 in mode 3 simply holds its count. The effect...
Page 262: Registers Description
XC82x Timer 0 and Timer 1 13.5 Registers Description Seven SFRs control the operations of Timer 0 and Timer 1. They can be accessed from both the standard (non-mapped) and mapped SFR area. Table 13-4 lists the addresses of these SFRs.
Page 263 XC82x Timer 0 and Timer 1 Field Bits Type Description [7:0] Timer 0/1 Low Register TLx holds the 5-bit prescaler value. TLx holds the lower 8-bit part of the 16-bit timer value. TLx holds the 8-bit timer value. TL0 holds the 8-bit timer value; TL1 is not used.
Page 264 XC82x Timer 0 and Timer 1 Field Bits Type Description Timer 0 Run Control Timer is halted Timer runs Timer 0 Overflow Flag Set by hardware when Timer 0 overflows. Cleared by hardware when the processor calls the interrupt service routine.
Page 265: Type Description
XC82x Timer 0 and Timer 1 Field Bits Type Description [1:0] Mode Select Bits 13-bit timer (M8048 compatible mode) 16-bit timer 8-bit auto-reload timer Timer 0 is split into two halves. TL0 is an 8-bit timer controlled by the standard Timer...
Page 266 XC82x Timer 0 and Timer 1 IEN0 Interrupt Enable Register Reset Value: 00 RMAP: X, PAGE: X Field Bits Type Description Timer 0 Overflow Interrupt Enable Timer 0 interrupt is disabled Timer 0 interrupt is enabled Timer 1 Overflow Interrupt Enable...
Page 267: System Information
MODPISEL2.T2EXIS. Among these sources, 4 of them are available as external pin. 2 of them are triggered internally by Out of Range 0 (ORC0) event and Out of Range 1 (ORC1) event from the ADC module. The Timer 2 pin assignment for XC82x is shown in Table 14-1.
Page 268 XC82x Timer 2 Table 14-1 Timer 2 Pin Functions in XC82x Pin/Sources Function Desciption Selected By P0.6 T2EX_0 Timer 2 External Trigger MODPISEL2.T2EXIS = 000 Input P0.4 T2EX_1 MODPISEL2.T2EXIS = 001 P1.0 T2EX_2 MODPISEL2.T2EXIS = 010 P2.0 T2EX_3 MODPISEL2.T2EXIS = 011 ORC0 event T2EX_4 MODPISEL2.T2EXIS = 100...
Page 269 XC82x Timer 2 Field Bits Type Description T2IS [4:3] Timer 2 Input Select Timer 2 Input T2_0 is selected. Timer 2 Input T2_1 is selected. Timer 2 Input T2_2 is selected. Reserved. Reserved Returns 0 if read; should be written with 0.
Page 270 Timer 2 External 14.2.4 IP interconnection In XC82x, T2EX_4 input and T2EX_5 input can be triggered by Out of Range 0 (ORC0) event and Out of Range 1 (ORC1) event from the ADC module respectively as shown in Table 14-4. ORCx will generate a rising edge signal to the T2EX input when there is an out of range event.
Page 271 XC82x Timer 2 14.3 Basic Timer Operations Timer 2 can be started by using TR2 bit by hardware or software. Timer 2 can be started by setting TR2 bit by software. If bit T2RHEN is set, Timer 2 can be started by hardware.
Page 272 XC82x Timer 2 Note: In counter mode, if the reload via T2EX and the count clock T2 are detected simultaneously, the reload takes precedence over the count. The counter increments its value with the following T2 count clock. PREN PCLK...
Page 273 XC82x Timer 2 underflow condition sets the TF2 flag and causes FFFF to be reloaded into the THL2 register. A fresh down counting sequence is started and the timer counts down as in the previous counting sequence. If bit T2RHEN is set, Timer 2 can only be started either by rising edge (T2REGS = 1) at pin T2EX and then proceed with the up counting, or be started by falling edge (T2REGS = 0) at pin T2EX and then proceed with the down counting.
Page 274: Capture Mode
XC82x Timer 2 14.5 Capture Mode In order to enter the 16-bit capture mode, bits CP/RL2 and EXEN2 in register T2CON must be set. In this mode, the down count function must remain disabled. The timer functions as a 16-bit timer and always counts up to FFFF , after which, an overflow condition occurs.
Page 275: Count Clock
XC82x Timer 2 PREN PCLK T2PRE C/T2=0 THL2 C/T2=1 Overflow Timer 2 Interrupt EXF2 EXEN2 T2EX Figure 14-3 Capture Mode 14.6 Count Clock The count clock for the auto-reload mode is chosen by the bit C/T2 in register T2CON. If C/T2 = 0, a count clock of f...
Page 276: External Interrupt Function
XC82x Timer 2 14.7 External Interrupt Function While the timer/counter function is disabled (TR2 = 0), it is still possible to generate a Timer 2 interrupt to the core via an external event at T2EX, as long as Timer 2 remains enabled (PMCON1.T2_DIS = 0).
Page 277 XC82x Timer 2 14.8 Registers Description All Timer 2 register names described in the following sections are referenced in other chapters of this document with the module name prefix “T2_”, e.g., T2_T2CON. The Timer 2 SFRs are located in the standard (non-mapped) SFR area.
Page 278 XC82x Timer 2 14.8.1 Mode Register The T2MOD is used to configure Timer 2 for various modes of operation. T2_T2MOD Timer 2 Mode Register Reset Value: 00 RMAP: 0, PAGE: X T2REGS T2RHEN EDGESEL PREN T2PRE DCEN Field Type Description...
Page 279: Type Description
XC82x Timer 2 Field Type Description T2REGS Edge Select for Timer 2 External Start The falling edge at Pin T2EX is selected. The rising edge at Pin T2EX is selected. 14.8.2 Control Register Control register T2CON is used to control the operating modes and interrupt of Timer 2.
Page 280 XC82x Timer 2 Field Type Description EXF2 Timer 2 External Flag In Capture/Reload Mode, this bit is set by hardware when a negative/positive transition occurs at pin T2EX, if bit EXEN2 = 1. This bit must be cleared by software.
Page 281 XC82x Timer 2 T2_RC2L Timer 2 Reload/Capture Register, Low Byte(C2 Reset Value: 00 RMAP: 0, PAGE: X Field Type Description [7:0] Reload/Capture Value [7:0] If CP/RL2 = 0, these contents are loaded into the timer register upon an overflow condition.
Page 282 XC82x Timer 2 T2_T2L Timer 2, Low Byte Reset Value: 00 RMAP: 0, PAGE: X THL2 Field Type Description THL2 [7:0] Timer 2 Value [7:0] These bits indicate the current 16-bit timer value. T2_T2H Timer 2, High Byte Reset Value: 00...
Page 283: Real Time Clock
15.1 Overview One of the XC82x’s perpherials is the Real-Time Clock (RTC) that, once started, can work independently of the state of the rest of the microcontroller. There are two possible clock sources for this real-time clock, mainly the 75 KHz internal oscillator and an external clock input via RTCCLK pin.
Page 284: Basic Timer Operation
RTCON register to 1. This enables the input clock into the real-time clock timer. 15.5 Real-Time Clock Modes In XC82x, the real-time clock operates in two modes. Mode 1 is the periodic wake-up mode that uses a 41-bit counter. In this mode, an internal oscillator of 75 KHz is used as User’s Manual 15-2 V1.0, 2010-02...
Page 285 Real-time clock is in stop mode. Note: In XC82x, there are only Mode 1 and 3. Mode 0 and Mode 2 are not available. 15.5.1 Mode 1: Periodic Wake-up Mode with 75 KHz Oscillator Clock Figure 15-1 shows Mode 1 of the real-time clock.
Page 286 2 CPU clock cycles. An update of the actual compared value is necessary once a captured event is triggered. In XC82x, it is recommended to trigger a capture event to read the value of the RTC counter (CNT). There is a potential of reading a wrong 32 bits real-time value while the RTC is in running mode as only 8 bit of data could be fetch at one time.
Page 287 Once started, the real-time clock continues counting until the bit RTCON.RTCC is cleared. The real-time clock is not affected by the idle mode of the XC82x, and continues counting in power down mode except in power down mode 1. In addition, the real-time clock will not stopped automatically if the bit OSC_CON.75KOSC2L status is set to 1.
Page 288 XC82x Real-Time Clock 15.7 Registers Description 14 SFRs are used to control the operation of real-time clock. They can be accessed from the standard (non-mapped) SFR area. The registers are described as follows. Table 15-4 lists the addresses of these SFRs.
Page 289 XC82x Real-Time Clock 15.7.1 Real-Time Clock Registers RTC_RTCON Real-Time Clock Control Register Reset Value: 02 RMAP: 0, PAGE: X SFRTC CFRTC ESRTC ECRTC RTCCT RTCC Field Bits Type Description RTCC Real-Time Clock Start/Stop Control Stop real-time clock Operation Start real-time clock Operation...
Page 290 Real-Time Clock Compare Flag This bit is set by hardware when there is a compare match and can only be cleared by software. A wake-up request is generated only if the XC82x is either in power down mode 2, 3 or 4. SFRTC...
Page 291 XC82x Real-Time Clock Field Bits Type Description CNT_VAL [7:0] Real-Time Clock Count Value [15:8] These bits represent counter value [15:8] of the current real-time clock timer. RTC_CNT2 [Mode 1 and Mode 3] Count Clock Register 2 Reset Value: 00 RMAP: 0, PAGE: X...
Page 292 XC82x Real-Time Clock with the captured CNT values after 2 CPU clock cycles. An update of the actual compared value is necessary once a captured event is triggered. RTC_RTCCR0 [Mode 1 and Mode 3] Real-Time Clock Compare/Capture Register 0(E7 Reset Value: 00...
Page 293 XC82x Real-Time Clock RTC_RTCCR2 [Mode 1 and Mode 3] Real-Time Clock Compare/Capture Register 2(EA Reset Value: 00 RMAP: 0, PAGE: X CC_VAL Field Bits Type Description CC_VAL [7:0] Compare/Capture Value [23:16] These bits represent compare/capture value [23:16] of the 32-bits value that could generate a compare interrupt when it matches with the current counter value.
Page 294 In modes 1, 2 and 3, the port behaves as an UART. Data is transmitted on TXD and received on RXD. Note: XC82x does not support mode 0 operation and therefore, RXDO line is not connected to any general purpose I/O port.
Page 295 XC82x UART Table 16-1 UART Pin Functions in XC82x Function Desciption Selected By P2.1 RXD_3 UART Receive Data Input 3 MODPISEL1.URRIS = 11 P0.6 TXD_0 UART Transmit Data Output 0 P0_ALTSEL0.P5 = 1 P0_ALTSEL1.P5 = 1 P0_ALTSEL2.P5 = 0 P1.0 TXD_1 UART Transmit Data Output 1 P1_ALTSEL0.P0 = 1...
Page 296 XC82x UART 16.2.3 Interrupt Events and Assignment Table 16-2 lists the interrupt event sources from the UART, and the corresponding event interrupt enable bit and flag bit. Table 16-2 UART Interrupt Events Event Event Interrupt Enable Bit Event Flag Bit Data Received –...
Page 297 XC82x UART The transmission cycle is activated by a write to SBUF. One machine cycle later, the data has been written to the transmit shift register with a 1 at the 9th bit position. For the next seven machine cycles, the contents of the transmit shift register are shifted right one position and a zero shifted in from the left so that when the MSB of the data byte is at the output position, it has a 1 and a sequence of zeros to its left.
Page 298 XC82x UART Transmit Receive Figure 16-1 Serial Interface, Mode 1, Timing Diagram User’s Manual 16-5 V1.0, 2010-02 UART, V 1.6...
Page 299 XC82x UART 16.3.3 Mode 2, 9-Bit UART, Fixed Baud Rate In mode 2, the UART behaves as a 9-bit serial port. A start bit (0), 8 data bits plus a programmable 9th bit and a stop bit (1) are transmitted on TXD or received on RXD. The 9th bit for transmission is taken from TB8 (SCON.3) while for reception, the 9th bit...
Page 300 XC82x UART Transmit Receive Figure 16-2 Serial Interface, Modes 2 and 3, Timing Diagram User’s Manual 16-7 V1.0, 2010-02 UART, V 1.6...
Page 301: Multiprocessor Communication
XC82x UART 16.4 Multiprocessor Communication Modes 2 and 3 have a special provision for multiprocessor communication using a system of address bytes with bit 9 = 1 and data bytes with bit 9 = 0. In these modes, 9 data bits are received. The 9th data bit goes into RB8. The communication always ends with one stop bit.
Page 302: Baud Rate Generation
XC82x UART 16.5 Baud Rate Generation There are several ways to generate the baud rate clock for the serial ports, depending on the mode in which they are operating. The baud rates in modes 0 and 2 are fixed, so they use the •...
Page 303 XC82x UART register BG each time it underflows. The duration between underflows depends on the ‘n’ value in the fractional divider, which can be selected by the bits BGL.FD_SEL. ‘n’ times out of 32, the timer counts one cycle more than specified by BR_VALUE. The prescaler is selected by the bits BCON.BRPRE.
Page 304 XC82x UART field BG.BR_VALUE. n/32 is defined by the fractional divider selection in bit field BG.FDSEL. The maximum baud rate that can be generated is limited to /32. Hence, for module PCLK clocks of 8 MHz and 24 MHz, the maximum achievable baud rate is 0.25 MBaud and 0.75 MBaud respectively.
Page 305 XC82x UART 16.5.3 Timer 1 In modes 1 and 3 of UART, Timer 1 can also be used for generating the variable baud rates. In theory, this timer could be used in any of its modes. But in practice, it should be set into auto-reload mode (Timer 1 mode 2), with its high byte set to the appropriate value for the required baud rate.
Page 306 XC82x UART 16.6 LIN Support in UART The UART module can be used to support the Local Interconnect Network (LIN) protocol for both master and slave operations. The LIN baud rate detection feature, which consists of the hardware logic for Break and Synch Field detection, provides the capability to detect the baud rate within LIN protocol using Timer 2.
Page 307 XC82x UART Byte field Start Stop (bit 0) (bit 7) Figure 16-5 The Structure of Byte Field The break is used to signal the beginning of a new frame. It is the only field that does not comply with Figure 16-5.
Page 308 XC82x UART The slave task will receive and transmit data when an appropriate ID is sent by the master: 1. Slave waits for Synch Break 2. Slave synchronizes on Synch Byte 3. Slave snoops for ID 4. According to ID, slave determines whether to receive or transmit data, or do nothing 5.
Page 309 XC82x UART 16.6.2.2 Initialization of Break/Synch Field Detection Logic The LIN baud rate detection feature provides the capability to detect the baud rate within the LIN protocol using Timer 2. Initialization consists of: • Serial port of the microcontroller set to Mode 1 (8-bit UART, variable baud rate) for communication.
Page 310 XC82x UART The baud rate range defined by different BGSEL settings is shown in Table 16-7. Table 16-7 BGSEL Bit Field Definition for Different Input Frequencies BGSEL Baud Rate Select for Detection PCLK /(2184*2^BGSEL) to /(72*2^BGSEL) pclk pclk 24 MHz 11 kHz to 333.3 kHz...
Page 311 XC82x UART 16.6.2.4 LIN Baud Rate Detection The baud rate detection for LIN is shown in Figure 16-8, the Header LIN frame consists of the: • SYN Break (13 bit times low) • SYN byte (55 • Protected ID field...
Page 312: Registers Description
XC82x UART 16.7 Registers Description Besides the SCON and SBUF registers, which can be accessed from both the standard (non-mapped) and mapped SFR area, the rest of the UART’s SFRs are located in SCU page 5 of the standard area. The bit field PAGE of SCU_PAGE register must be programmed before accessing these registers.
Page 313: Uart Registers
XC82x UART 16.7.1 UART Registers UART contains the two Special Function Registers (SFRs), SCON and SBUF. SCON is the control register and SBUF is the data register. On reset, both SCON and SBUF return . The serial port control and status register is the SFR SCON. This register contains not only the mode selection bits, but also the 9th data bit for transmit and receive (TB8 and RB8) and the serial port interrupt bits (TI and RI).
Page 314 XC82x UART Field Bits Type Description Transmit Interrupt Flag This is set by hardware at the end of the 8th bit in mode 0, or at the beginning of the stop bit in modes 1, 2, and 3. Must be cleared by software.
Page 315 XC82x UART 16.7.2 Baud-rate Generator Control and Status Registers PCON Power Control Register Reset Value: 00 RMAP: X, PAGE: X SMOD IDLE Field Bits Type Description SMOD Double Baud Rate Enable Do not double the baud rate of serial interface in modes 1, 2 and 3.
Page 316 XC82x UART Field Bits Type Description BRPRE [3:1] Prescaler Bit Selects the input clock for which is derived from the peripheral clock. PCLK PCLK PCLK PCLK PCLK PCLK Others: reserved BRDIS Baud Rate Detection Disable Break/Synch detection is enabled. Break/Synch detection is disabled.
Page 317 XC82x UART Field Bits Type Description EOFSYN End of SYN Byte Interrupt Flag This bit is set by hardware and can only be cleared by software. End of SYN Byte is not detected. End of SYN Byte is detected. ERRSYN...
Page 318 XC82x UART Field Bits Type Description FD_SEL [4:0] Fractional Divider Selection Selects the fractional divider to be n/32, where n is the value of FD_SEL and is in the range of 0 to 31. For example, writing 0001 to FD_SEL selects the fractional divider to be 1/32.
Page 319: System Information
Flexible control via interrupt service routines or polling 17.2 System Information This section provides system information relevant to the IIC. 17.2.1 Pinning The IIC pin assignment for XC82x is shown in Table 17-1. Table 17-1 IIC Pin Functions in XC82x Function Desciption Selected By P0.4 SCL_0...
Page 320: Clocking Configuration
XC82x Inter-IC Bus Since SCL and SDA have input and output functions within the same set of pin selected, the input and output signal selection is done using just the Px_ALTSELn signals from the GPIO module. No separate input selection control (PISEL) is required..
Page 321 XC82x Inter-IC Bus Field Bits Type Description IIC_DIS IIC Disable Request. Active high. IIC is in normal operation. Request to disable the IIC. (default) Reserved Returns 0 if read; should be written with 0. 17.2.3 Interrupt Events and Assignment Table 17-2 lists the interrupt event source from the IIC, and the corresponding event interrupt enable bit and flag bit.
Page 322: Status Code
XC82x Inter-IC Bus 17.3 Status Code The state of the IIC is defined by the 5-bit status code in STAT register. When STAT contains the status code F8 , no relevant status information is available, no interrupt is generated and the IFLG bit in the CNTR register is not set. All other status codes correspond to a defined state of the IIC.
Page 323 XC82x Inter-IC Bus Table 17-4 Status Code Value of Status STAT register STOP or repeated START mode received in slave mode Slave address and read bit received, ACK transmitted Arbitration lost in address as master, slave address and read bit...
Page 324: Clock Synchronization
XC82x Inter-IC Bus Table 17-5 Baud Rate Selection Baud Rate = 100 KBaud Baud Rate = 400 KBaud PREDIV BRP+1 PREDIV BRP+1 PCLK 8 MHz 1 (1 4 (4 1 (1 1 (1 24 MHz 1 (1 12 (C 1 (1...
Page 325: Software Reset
XC82x Inter-IC Bus 17.7 Software Reset A software reset may be applied to the IIC module by writing any value to register SRST (address DF ). This sets the IIC back to idle (STAT set to F8 ) and sets the STP, STA and IFLG bits of the CNTR register to 0.
Page 326 XC82x Inter-IC Bus Table 17-6 Status Code after Address is Transmitted in Master Transmit Mode Code IIC State CPU Response Next IIC Action Addr + W, For 7-bit address: ACK received Write byte to DATA, clear Transmit data byte, IFLG...
Page 327 XC82x Inter-IC Bus If 10-bit addressing is being used, then after the first part of a 10-bit address plus the Write bit have been successfully transmitted, the status code will be 18 or 20 After this interrupt has been serviced and the second part of the address transmitted, the...
Page 328 XC82x Inter-IC Bus Table 17-8 Status Code after Data is Transmited in Master Transmit Mode Code IIC State CPU Response Next IIC Action Data byte Write byte to DATA, clear Transmit data byte, transmitted, IFLG receives ACK ACK received Or set STA, clear IFLG...
Page 329 XC82x Inter-IC Bus Table 17-9 Status Code after Address is Transmitted in Master Receive Mode Code IIC State CPU Response Next IIC Action Addr + R Clear IFLG, AAK = 0 Receive data byte, transmit transmitted, ACK not ACK received...
Page 330 XC82x Inter-IC Bus After each data byte has been received, IFLG will be set and one of three status codes will be in the STAT register: Table 17-10 Status Code after Data is Received in Master Receive Mode Code IIC State...
Page 331 XC82x Inter-IC Bus Slave transmit mode can also be entered directly from a master mode if arbitration is lost in master mode during the transmission of an address and the slave address and Read bit are received. The status code in the STAT register will then be B0 The data byte to be transmitted should then be loaded into the DATA register and IFLG cleared.
Page 332 XC82x Inter-IC Bus If the AAK bit is cleared to 0 during a transfer, the IIC will transmit a not acknowledge bit (high level on SDA) after the next byte is received, and set the IFLG bit. The STAT register will contain status code 88...
Page 333 XC82x Inter-IC Bus 17.9 Registers Description The IIC Special Function Registers are accessed from the standard (non-mapped) SFR area. Table 17-11 lists the IIC registers with their addresses. Table 17-11 Register Map Address Register Description IIC_ADDR Slave Address Register IIC_DATA...
Page 334 XC82x Inter-IC Bus 17.9.1 Slave Address Registers The ADDR register contains the bit to enable the general call address option and the device address of the IIC in 7-bit addressing mode. For 10-bit addressing, part of the address bits is located in ADDRX register.
Page 335: Data Register
XC82x Inter-IC Bus The ADDRX register contains the lower 8-bit slave address of the device in 10-bit addressing mode. IIC_ADDRX Extended Slave Address Register Reset Value: 00 RMAP: 0, PAGE: X SLAX Field Bits Type Description SLAX [7:0] Extended Slave Address For 10-bit addressing, SLAX contains the lower 8-bit address of the IIC when in slave mode.
Page 336 XC82x Inter-IC Bus 17.9.3 Control Register The CNTR register is used to configure the IIC and generate START and STOP conditions. It also contains the interrupt status flag. IIC_CNTR Control Register Reset Value: 00 RMAP: 0, PAGE: X ENAB IFLG...
Page 337: Type Description
XC82x Inter-IC Bus Field Bits Type Description Master Mode Stop When the STP bit is set to 1, the IIC will transmit a STOP condition. If the STP bit is set while the IIC is in slave mode, no STOP condition will be transmitted on the IIC bus but the IIC behaves as if a STOP condition has been received.
Page 338 XC82x Inter-IC Bus Field Bits Type Description [1:0] Reserved Returns 0 if read; should be written with 0. 17.9.4 Status Register The read-only STAT register stores the 5-bit status code of the IIC. IIC_STAT Status Register [Read Mode] Reset Value: F8...
Page 339 XC82x Inter-IC Bus 17.9.5 Baud Rate Control Register The write-only BRCR register controls the sampling frequency of the IIC and the baud rate of the IIC in master mode. IIC_BRCR Baud Rate Control Register [Write Mode] Reset Value: 00 RMAP: 0, PAGE: X...
Page 340 XC82x Inter-IC Bus Field Bits Type Description SRST [7:0] Software Reset Writing any value to the SRST bit field triggers a soft reset on the IIC. User’s Manual 17-22 V1.0, 2010-02 IIC, V1.1...
Page 341 XC82x High-Speed Synchronous Serial Interface High-Speed Synchronous Serial Interface 18.1 Overview The High-Speed Synchronous Serial Interface (SSC) supports both full-duplex and half-duplex serial synchronous communication. The serial clock signal can be generated by the SSC itself (Master Mode) through its own 16-bit baud rate generator, or can be received from an external master (Slave Mode).
Page 342: System Information
Register RB Internal Bus Figure 18-1 SSC Block Diagram 18.2 System Information This section provides system information relevant to the SSC. 18.2.1 Pinning The SSC pin assignment for XC82x is shown in Table 18-1. User’s Manual 18-2 V1.0, 2010-02 SSC, V1.4...
Page 343 XC82x High-Speed Synchronous Serial Interface Table 18-1 SSC Pin Functions in XC82x Function Desciption Selected By P0.4 SCK_0 SSC Clock Input/Output For Input: MODPISEL.CIS = 0 For Output: P0_ALTSEL0.P4 = 0 P0_ALTSEL1.P4 = 1 P0_ALTSEL2.P4 = 0 P2.2 SCK_1 SSC Clock Input For Input: MODPISEL.CIS = 1...
Page 344 XC82x High-Speed Synchronous Serial Interface Table 18-1 SSC Pin Functions in XC82x Function Desciption Selected By P0.1 MRST_2 SSC Master Receive Input For Input: /Slave Transmit Output MODPISEL.MIS = 10 For Output: P0_ALTSEL0.P1 = 0 P0_ALTSEL1.P1 = 1 P0.0 MRST_3...
Page 345 XC82x High-Speed Synchronous Serial Interface Field Bits Type Description [5:3] Slave Mode Receive Input Select 000 SSC Slave Receiver Input 0 is selected. 001 SSC Slave Receiver Input 1 is selected. 010 SSC Slave Receiver Input 2 is selected. 011 SSC Slave Receiver Input 3 is selected.
Page 346: Clocking Configuration
XC82x High-Speed Synchronous Serial Interface 18.2.2 Clocking Configuration The SSC runs on the PCLK at a frequency of either 8 MHz or 24 MHz. If the SSC functionality is not required at all, it can be completely disabled by gating off its clock input for maximal power reduction.
Page 347 XC82x High-Speed Synchronous Serial Interface 18.2.3 Interrupt Events and Assignment Table 18-2 lists the interrupt event sources from the SSC, and the interrupt node assignment for each SSC interrupt source. Note: All SSC interrupt enable bits and flags are located at the node level.
Page 348: General Operation
XC82x High-Speed Synchronous Serial Interface Field Bits Type Description [5:3] Reserved Returns 0 if read; should be written with 0. 18.3 General Operation The SSC supports full-duplex and half-duplex synchronous communication up to 12 MBaud (@ 24 MHz module clock). The serial clock signal can be generated by the SSC itself (Master Mode) or can be received from an external master (Slave Mode).
Page 349 XC82x High-Speed Synchronous Serial Interface will be activated. If no further transfer is to take place (TB is empty), CON.BSY will be cleared at the same time. Software should not modify CON.BSY, as this flag is hardware controlled. Note: The SSC starts transmission and sets CON.BSY minimum two clock cycles after transmit data is written into TB.
Page 350: Full-Duplex Operation
XC82x High-Speed Synchronous Serial Interface CON. CON. Shift Clock MS_CLK/SS_CLK Pins MTSR/MRST Transmit Data First Last Latch Data Shift Data Figure 18-2 Serial Clock Phase and Polarity Options 18.3.2 Full-Duplex Operation The various devices are connected through three lines. The definition of these lines is always determined by the master: the line connected to the master’s data output line...
Page 351 XC82x High-Speed Synchronous Serial Interface Master Device #1 Device #2 Slave Shift Register Shift Register MTSR Transmit MTSR Receive MRST MRST Clock Clock Clock Device #3 Slave Shift Register MTSR MRST Clock Figure 18-3 SSC Full-Duplex Configuration The data output pins MRST of all slave devices are connected together onto the one...
Page 352 XC82x High-Speed Synchronous Serial Interface the slave device from which it expects data either by separate select lines or by sending a special command to this slave. After performing the necessary initialization of the SSC, the serial interfaces can be enabled.
Page 353: Half-Duplex Operation
XC82x High-Speed Synchronous Serial Interface 18.3.3 Half-Duplex Operation In a Half-Duplex Mode, only one data line is necessary for both receiving and transmitting of data. There are two port configuration options for Half-Duplex Mode. The first option uses all the three pins but with the data exchange line connected to both the MTSR and MRST pins of each device;...
Page 354: Continuous Transfers
XC82x High-Speed Synchronous Serial Interface The Half-Duplex Mode port configuration using three pins is shown in Figure 18-4. Master Device #1 Device #2 Slave Transmit Shift Register Shift Register MTSR MTSR MRST MRST Clock Clock Clock Common Transmit/ Device #3...
Page 355 XC82x High-Speed Synchronous Serial Interface 18.3.5 Baud Rate Generation The serial channel SSC has its own dedicated 16-bit baud-rate generator with 16-bit reload capability, allowing baud rate generation independent of the timers. Figure 18-5 shows the baud-rate generator. 16-Bit Reload Register...
Page 356: Error Detection Mechanisms
XC82x High-Speed Synchronous Serial Interface Table 18-3 Typical Baud Rates of the SSC ( = 24 MHz) hw_clk Reload Value Baud Rate (= Deviation MS_CLK/SS_CLK 0000 12 MBaud (only in Master Mode) 0.0% 0001 6 MBaud 0.0% 0005 2 MBaud 0.0%...
Page 357 XC82x High-Speed Synchronous Serial Interface Bits in Register & Transmit Error & Receive > 1 Error Error Interrupt & Phase Error & Baud rate Error Figure 18-6 SSC Error Interrupt Control A Receive Error (Master or Slave Mode) is detected when a new data frame is completely received but the previous data was not read out of the receive buffer register RB.
Page 358 XC82x High-Speed Synchronous Serial Interface same baud rate as the master device. This feature detects false additional, or missing pulses on the clock line (within a certain frame). Note: If this error condition occurs and bit CON.AREN = 1, an automatic reset of the SSC will be performed in case of this error.
Page 359 XC82x High-Speed Synchronous Serial Interface 18.4 Interrupts The three SSC interrupts can be separately enabled or disabled by setting or clearing their corresponding enable bits in SFR SCU_MODIEN. For a detailed description of the various interrupts see Section 18.3. An overview is...
Page 360: Register Description
XC82x High-Speed Synchronous Serial Interface 18.5 Register Description The SSC Special Function Registers are accessed from the standard (non-mapped) SFR area. The addresses of the SFRs are listed in Table 18-5. Table 18-5 Register Map Address Register CONL CONH User’s Manual 18-20 V1.0, 2010-02...
Page 361: Configuration Register
XC82x High-Speed Synchronous Serial Interface 18.5.1 Configuration Register The operating mode of the serial channel SSC is controlled by the control register CON. This register contains control bits for mode and error check selection, and status flags for error identification. Depending on bit EN, either control functions or status flags and master/slave control are enabled.
Page 362 XC82x High-Speed Synchronous Serial Interface Field Type Description Loop Back Control Normal output. Receive input is connected with transmit output (half-duplex mode). SSC_CONH Control Register High [Programming Mode] Reset Value: 00 RMAP: 0, PAGE: X AREN Field Type Description Transmit Error Enable Ignore transmit errors.
Page 363 XC82x High-Speed Synchronous Serial Interface Field Type Description Enable Bit = 0 Transmission and reception disabled. Access to control bits. Reserved Returns 0 if read; should be written with 0. User’s Manual 18-23 V1.0, 2010-02 SSC, V1.4...
Page 364 XC82x High-Speed Synchronous Serial Interface CON.EN = 1: Operating Mode SSC_CONL Control Register Low [Operating Mode] Reset Value: 00 RMAP: 0, PAGE: X Field Type Description [3:0] Bit Count Field Shift counter is updated with every shift bit. Note: This bit field is not to be written to.
Page 365 XC82x High-Speed Synchronous Serial Interface Field Type Description Phase Error Flag No error. Received data changes around sampling clock edge. Baud Rate Error Flag No error. More than factor 2 or 0.5 between slave’s actual and expected baud rate. Busy Flag Set while a transfer is in progress.
Page 366 XC82x High-Speed Synchronous Serial Interface 18.5.2 Baud Rate Timer Reload Register The SSC baud rate timer reload register BR contains the 16-bit reload value for the baud rate timer. SSC_BRL Baud Rate Timer Reload Register Low (AE Reset Value: 00...
Page 367 XC82x High-Speed Synchronous Serial Interface SSC_TBL Transmitter Buffer Register Low Reset Value: 00 RMAP: 0, PAGE: X TB_VALUE Field Type Description TB_VALUE [7:0] Transmit Data Register Value TB_VALUE is the data value to be transmitted. Unselected bits of TB are ignored during transmission.
Page 368 XC82x LED and Touch-Sense Controller LED and Touch-Sense Controller This chapter describes the LEDTSCU. 19.1 Overview The LED and Touch-sense control unit (LEDTSCU) provides for up to eight line pins and up to eight column pins, time-multiplexed control for LED driving and touchpad sensing on single pin.
Page 369 This section provides system information relevant to the LEDTSCU. 19.2.1 Pinning Table 19-1 describes how to enable/select the particular LED or touch-sense pin function for XC82x. Table 19-1 XC82x Pin Functions and Selection Function Desciption Selected By P0.0 TSIN0/LINE0 Touch-sense input 0/ P0_ALTSEL0.P0 = 1...
Page 370: Clocking Configuration
XC82x LED and Touch-Sense Controller Table 19-1 XC82x Pin Functions and Selection Function Desciption Selected By P1.2 COL2_0 LED column 2 P1_ALTSEL0.P2 = 1 P1_ALTSEL1.P2 = 0 P0.6 COL2_1 LED column 2 P0_ALTSEL0.P6 = 1 P0_ALTSEL1.P6 = 0 P0_ALTSEL2.P6 = 1 P1.3...
Page 371 XC82x LED and Touch-Sense Controller PMCON1 Peripheral Management Control Register 1(EF Reset Value: DF RMAP: 0, PAGE: 1 IIC_DIS LTS_DIS MDU_DIS T2_DIS CCU_DIS SSC_DIS ADC_DIS Field Bits Type Description LTS_DIS LEDTSCU Disable Request. Active high. LEDTSCU is in normal operation.
Page 372 XC82x LED and Touch-Sense Controller Table 19-4 LEDTSCU Interconnections LEDTSCU Function/Signal Connected Other Module Function/Signal Compare match (o): LEDTS_CM ADC external trigger (i): REQTR0G, REQTR1G Time slice interrupt (o): LEDTS_TSI ADC external trigger (i): REQTR0H, REQTR1H 19.2.5 Debug Suspend Control The LEDTSCU timers/counters, LEDTS-counter and TS-counter, can be enabled (together) for suspend operation when debug Monitor Mode becomes active.
Page 373 XC82x LED and Touch-Sense Controller To allow flexible duration of activation of LED columns and/or touch-sense oscillation counting, the duty cycle of column enable and pad oscillation enable can be adjusted for each time slice. Figure 19-1 shows an example for a LED matrix configuration with touch pads. The configuration in this example is 8 X 4 LED matrix with 4 touch pad turns (here: 6 touch pads) enabled in sequence by hardware.
Page 374 XC82x LED and Touch-Sense Controller One complete period Frame 0 Frame 1 Frame 2 Frame 3 5.3*5 us - 2.01*5 ms C 2 C1 TS C3 C1 C 0 C3 C2 C 0 TS C 2 C1 LTS_fn COLA pad _turn_0...
Page 375 XC82x LED and Touch-Sense Controller 19.4 LED Driving The control provided for LED driving is mainly for LED column selection – where one column is enabled at a time. It is required for interrupt-based software handling to control LED enabling per selected column. Up to eight LED columns are supported, and up to eight LEDs can be enabled per column.
Page 376 XC82x LED and Touch-Sense Controller which is equal to the reset value. Within each time frame, the sequence of LED column enabling always start from the most-significant enabled column (column with higher numbering). Example in case of four LED columns enabled, in ordered sequence: •...
Page 377 XC82x LED and Touch-Sense Controller 19.4.1 LED Pin Assignment and Current Capability One LED column pin is enabled at a time within each configured time slice duration to control up to eight LEDs. The assignment of COL[x] to pins is configurable to suit various use cases.
Page 378 XC82x LED and Touch-Sense Controller 19.5 Touchpad Sensing Figure 19-3 shows the pin oscillation control unit, which is actually integrated with the standard GPIO pad. An active pad turn (pad_turn_x) is defined for the touch-sense input pin TSIN[x] as the duration within the touch-sense time slice where the TS-counter is counting.
Page 379 XC82x LED and Touch-Sense Controller The touch-sense function is active in the last time slice of a time frame. Refer to Section 19.3, and Section 19.4 for more details on time slice allocation and configuration. TS-counter input Input high threshold “ts_extended”...
Page 380 XC82x LED and Touch-Sense Controller 19.5.1 Finger Sensing When a finger is placed on the sensor pad, it increases the pad capacitance and frequency of oscillation on pad is reduced. The pad oscillation frequency without finger is typically expected in the approximate range 0.25 MHz to 0.5 MHz. With finger on the sensor, the pad oscillation frequency is typically expected in the approximate range 0.125 MHz to 0.25 MHz.
Page 381 XC82x LED and Touch-Sense Controller 19.6 Time-Multiplexed LED and Touch-Sense Function on Pin Some hints are provided regarding the time-multiplexed usage of a pin for LED and touch-sense function: • The maximum number of LED columns = 7 when touch-sense function is also enabled.
Page 382 XC82x LED and Touch-Sense Controller 19.7 Function Enabling and Control Hints It is recommended to set up all configuration for the LEDTSCU in all SFRs before write LTS_GLOBCTL0 SFR to enable and start LED and/or touch-sense function(s). Note: SFR bits especially affecting the LEDTS-counter configuration for LED/touch- sense function can only be written when the counter is not running i.e.
Page 383 XC82x LED and Touch-Sense Controller Interpretation of Bit Field FNCOL The handling by software in each time slice includes to update the line value and compare value to be activated (shadow-transferred) in the next time slice. The FNCOL bit field provides information on the function/column active in the previous time slice.
Page 384 XC82x LED and Touch-Sense Controller LED drive active duration: (19.4) × ÷ LED Drive Active Duration TSD Compare_VALUE 2 Touch-sense drive active duration: (19.5) × ÷ Touch-sense Drive Active Duration Compare_VALUE – User’s Manual 19-17 V1.0, 2010-02 LEDTSCU, V 1.2.1...
Page 385 XC82x LED and Touch-Sense Controller 19.9 LEDTSCU Pin Control The user may flexibly assign pins as provided by GPIO-SFR ALTSEL, for the LEDTSCU functions: • COL[x] (for LED column control) • LINE[x]/TSIN[x] (for LED line control or touch-sensing) Refer also to Section 19.4...
Page 386 XC82x LED and Touch-Sense Controller Touch-sense enable over -rule && pad _turn_x Touch-sense disable pull over -rule Touch-sense pull -up only Definition : P UDE N &S E L P ull Control GP IO func tion Touch-sense open -drain enable...
Page 387 XC82x LED and Touch-Sense Controller 19.11 Registers Description The LEDTSCU Special Function Registers are accessed from the standard (non- mapped) SFR area. Table 19-7 lists the SFRs and corresponding address. Table 19-7 Register Map Address Register LTS_GLOBCTL0 LTS_COMPARE LTS_LDLINE LTS_LDTSCTL...
Page 388 XC82x LED and Touch-Sense Controller 19.11.1 Global Control and Status There are three registers for global control and status. LTS_GLOBCTL0 Global Control Register 0 Reset Value: 00 RMAP: 0, PAGE: X LD_EN TS_EN CLK_PS Field Bits Type Description CLK_PS [5:0]...
Page 389: Type Description
XC82x LED and Touch-Sense Controller LTS_GLOBCTL1 Global Control Register 1 Reset Value: 00 RMAP: 0, PAGE: X ITS_EN ITF_EN CLKSEL FNCOL Field Bits Type Description FNCOL [2:0] Previous Active Function/LED Column Status Shows the active function / LED column in the previous time slice.
Page 390 XC82x LED and Touch-Sense Controller LTS_COMPARE Time Slice Compare Shadow Register(D4 Reset Value: 00 RMAP: 0, PAGE: X SHD_CMP Field Bits Type Description SHD_CMP [7:0] Compare Value for Time Slice to Shadow- Transfer This value is shadow-transferred to the time slice compare register on start of each new time slice.
Page 391 XC82x LED and Touch-Sense Controller 19.11.2 Function Control Registers These registers provide controls for the LED drive and touch-sense functions. LTS_LDTSCTL LED and Touch-Sense Control Register(D6 Reset Value: 00 RMAP: 0, PAGE: X NR_LEDCOL COLLEV NR_PADT TSOEXT Field Bits Type Description...
Page 392 XC82x LED and Touch-Sense Controller Field Bits Type Description NR_LEDCOL [7:5] Number of LED Columns Defines the number of LED columns. 1 LED column 2 LED columns 3 LED columns 4 LED columns 5 LED columns 6 LED columns 7 LED columns 8 LED columns (max.
Page 393 XC82x LED and Touch-Sense Controller LTS_TSCTL Touch-Sense Control Register Reset Value: 00 RMAP: 0, PAGE: X TSCTROV TSCTRSA TSCTRR EPULL PADTSW PADT Field Bits Type Description PADT [2:0] Touch-Sense Pad Turn (Input Pin) This is the next or currently active pad turn (touch- sense input pin).
Page 394 XC82x LED and Touch-Sense Controller Field Bits Type Description TSCTRSAT Saturation of TS-Counter Disable Enable. TS-counter stops counting in the current time slice when it reaches FF Counter starts to count again on new pad turn, triggered on compare match.
Page 395: Capture/Compare Unit 6 (Ccu6)
XC82x Capture/Compare Unit 6 (CCU6) Capture/Compare Unit 6 (CCU6) The CCU6 is a high-resolution 16-bit capture and compare unit with application specific modes, mainly for AC drive control. Special operating modes support the control of Brushless DC-motors using Hall sensors or Back-EMF detection. Furthermore, block commutation and control mechanisms for multi-phase machines are supported.
Page 396: Feature Set Overview
XC82x Capture/Compare Unit 6 (CCU6) 20.1.1 Feature Set Overview This section gives an overview over the different building blocks and their main features. Timer 12 Block Features • Three capture/compare channels, each channel can be used either as capture or as compare channel •...
Page 397: Block Diagram
XC82x Capture/Compare Unit 6 (CCU6) 20.1.2 Block Diagram The Timer T12 can operate in capture and/or compare mode for its three channels. The modes can also be combined (e.g. a channel operates in compare mode, whereas another channel operates in capture mode). The Timer T13 can operate in compare mode only.
Page 398 XC82x Capture/Compare Unit 6 (CCU6) 20.1.3 Register Overview For the generation of the overall register table, the prefix “CCU6x_” has to be added to the register names in this table to identify the registers of different CCU6 modules that are implemented. In this naming convention, x indicates the module number.
Page 399 XC82x Capture/Compare Unit 6 (CCU6) Table 20-1 CCU6 Module Register Summary Short Name Description Offset Reset Value Page General Registers PISEL0L Port Input Select Register Low Page 20-127 PISEL0H Port Input Select Register High Page 20-128 PISEL2 Port Input Select Register 2...
Page 400 XC82x Capture/Compare Unit 6 (CCU6) Table 20-1 CCU6 Module Register Summary (cont’d) Short Name Description Offset Reset Value Page CC61SRL Capture/Compare Shadow Register Page 20-47 Channel CC61 Low CC61SRH Capture/Compare Shadow Register Page 20-47 Channel CC61 High CC62SRL Capture/Compare Shadow Register...
Page 401 XC82x Capture/Compare Unit 6 (CCU6) Table 20-1 CCU6 Module Register Summary (cont’d) Short Name Description Offset Reset Value Page CC63RL Compare Register for Timer 13 Low Page 20-83 CC63RH Compare Register for Timer 13 High Page 20-83 CC63SRL Compare Shadow Register for Timer 13...
Page 402 20.2 System Information This section provides system information relevant to the CCU6. 20.2.1 Pinning The CCU6 pin assignment for XC82x is shown in Table 20-2. Table 20-2 CCU6 Pin Functions and Selection Function...
Page 403 XC82x Capture/Compare Unit 6 (CCU6) Table 20-2 CCU6 Pin Functions and Selection Function Desciption Selected By P0.0 CCPOS0_0 Input signals for CCPOS0 CCU6_PISEL0H.ISPOS0 = 00 P2.0 CCPOS0_1 CCU6_PISEL0H.ISPOS0 = 01 P2.3 CCPOS0_2 CCU6_PISEL0H.ISPOS0 = 10 P0.1 CCPOS1_0 Input signals for CCPOS1 CCU6_PISEL0H.ISPOS1 = 00...
Page 404 XC82x Capture/Compare Unit 6 (CCU6) Table 20-2 CCU6 Pin Functions and Selection Function Desciption Selected By P1.3 CC61_0 Compare outputs for channel P1_ALTSEL0.P3 = 0 CC61 P1_ALTSEL1.P3 = 1 P0.1 CC61_1 P0_ALTSEL0.P1 = 1 P0_ALTSEL1.P1 = 1 P1.2 COUT61_0 P1_ALTSEL0.P2 = 0 P1_ALTSEL1.P2 = 1...
Page 405 XC82x Capture/Compare Unit 6 (CCU6) Field Bits Type Description CTRAPIS [1:0] CCU6 CTRAP Input Selection CCU6 CTRAP Input Pin CTRAP_0 is selected. CCU6 CTRAP Input Pin CTRAP_1 is selected. CCU6 CTRAP Input Pin CTRAP_2 is selected. Out of Range Channel 3 event on Input Pin CTRAP_3 is selected.
Page 406 XC82x Capture/Compare Unit 6 (CCU6) Field Bits Type Description IST13HR1 [7:5] CCU6 T13HR Port Pin Input Select 000 T13HR Input Pin T13HR_0 is selected. 001 T13HR Input Pin T13HR_1 is selected. 010 T13HR Input Pin T13HR_2 is selected. 011 T13HR Input Pin T13HR_3 is selected.
Page 407 XC82x Capture/Compare Unit 6 (CCU6) 20.2.3 Interrupt Events and Assignment Table 20-3 lists the interrupt event sources from the CCU6, and the corresponding event interrupt enable bit and flag bit. Table 20-3 CCU6 Interrupt Events Event Event Interrupt Enable Bit Event Flag Bit...
Page 408 XC82x Capture/Compare Unit 6 (CCU6) MODIEN Peripheral Interrupt Enable Register (F7 Reset Value: 07 RMAP: 0, PAGE: 3 CCU6SR3 CCU6SR2 RIREN TIREN EIREN Field Bits Type Description CCU6SR2EN CCU6 SR2 Enable CCU6 SR2 interrupt service request is disabled CCU6 SR2 interrupt service request is enabled...
Page 409 XC82x Capture/Compare Unit 6 (CCU6) 20.2.4 IP Interconnection The CCU6 has interconnection to other peripherals enabling higher level of automation without requiring software. Table 20-5 CCU6 Outputs Interconnection CCU6 Function/Signal Connected Other Module Function/Signal Timer 12 output signals T12 period match (o): T12PM...
Page 410 XC82x Capture/Compare Unit 6 (CCU6) Table 20-6 CCU6 Inputs Interconnection CCU6 Connected Other Module Selected By Function/Signal Function/Signal CCU6 input (i): CC62 CCU6 SR2 output (o): CCU6_PISEL0L.ISCC62 = 10 CCU6_SR2 ADC Boundary event 2 (o): CCU6_PISEL0L.ISCC62= 11 ADC_BF2 CCU6 input (i): T12HR CCU6 SR2 output (o): CCU6_PISEL0H.IST12HR = 01...
Page 411 Debug-Suspend signal is active (MMCR2.DSUSP = 1), Timer T12 and Timer T13 of CCU6 module in XC82x can be suspended based on the settings of their corresponding module suspend bits in register MODSUSP. The definition of this register...
Page 412 XC82x Capture/Compare Unit 6 (CCU6) State Bits Capture/Compare CC60ST Channel CC60 Dead-Time Timer T12 Capture/Compare Control CC61ST Logic Channel CC61 Output Modulation Capture/Compare CC62ST Channel CC62 Input and Control/Status Logic T12HR CC6xIN CCPOSx CCU6_MCA05507 Figure 20-3 Overview Diagram of the Timer T12 Block User’s Manual...
Page 413 XC82x Capture/Compare Unit 6 (CCU6) 20.3.1 T12 Overview Figure 20-4 shows a detailed block diagram of Timer T12. The functions of the timer T12 block are controlled by bits in registers TCTR0L, TCTR0H, TCTR2L, TCTR2H, TCTR4L, TCTR4H, PISEL0L and PISEL0H.
Page 414 XC82x Capture/Compare Unit 6 (CCU6) defined by T12PR. In Center-Aligned mode, the count direction of T12 is set from ‘up’ to ‘down’ after it has reached the period value (please note that in this mode, T12 exceeds the period value by one before counting down). In both cases, signal T12_PM (T12 Period Match) is generated.
Page 415: Clock Selection
XC82x Capture/Compare Unit 6 (CCU6) 20.3.2 T12 Counting Scheme This section describes the clocking and counting capabilities of T12. 20.3.2.1 Clock Selection The input clock of Timer T12 is derived from the internal module clock through a programmable prescaler and an optional 1/256 divider. The resulting prescaler factors...
Page 416 XC82x Capture/Compare Unit 6 (CCU6) Period Value Period Zero T12 Count Match Match Zero CDIR CC6x Value n+1 Value n+2 Shadow Transfer CCU6_MCT05509 Figure 20-5 T12 Operation in Edge-Aligned Mode As a result, in Edge-Aligned mode, the timer period is given by: = <Period-Value>...
Page 417 XC82x Capture/Compare Unit 6 (CCU6) <Period Value> + 1 Period Value Zero Period Period T12 Count Match Match Match Zero Down Down CDIR CC6x Value n Value n+1 Value n+1 Value n+2 Shadow Transfer Shadow Transfer CCU6_MCT05510 Figure 20-6 T12 Operation in Center-Aligned Mode Note: Bit CDIR changes with the next timer clock event after the one-match or the period-match.
Page 418: Single-Shot Mode
XC82x Capture/Compare Unit 6 (CCU6) 20.3.2.3 Single-Shot Mode In Single-Shot Mode, the timer run bit T12R is cleared by hardware. If bit T12SSC = 1, the timer T12 will stop when the current timer period is finished. In Edge-Aligned mode, T12R is cleared when the timer becomes zero after having...
Page 419 XC82x Capture/Compare Unit 6 (CCU6) 20.3.3 T12 Compare Mode Associated with Timer T12 are three individual capture/compare channels, that can perform compare or capture operations with regard to the contents of the T12 counter. The capture functions are explained in Section 20.3.5.
Page 420 XC82x Capture/Compare Unit 6 (CCU6) 20.3.3.2 Channel State Bits Associated with each (compare) channel is a State Bit, CMPSTATL.CC6xST, holding the status of the compare (or capture) operation (see Figure 20-10). In compare mode, the State Bits are modified according to a set of switching rules, depending on the current status of timer T12.
Page 421 XC82x Capture/Compare Unit 6 (CCU6) In addition, each state bit can be set or cleared by software via the appropriate set and reset bits in register CMPMODIFL, CMPMODIFH, MCC6xS and MCC6xR. The input signals CCPOSx are used in hysteresis-like compare mode, whereas in normal compare mode, these inputs are ignored.
Page 422 XC82x Capture/Compare Unit 6 (CCU6) while the timer is running. This change is performed via a software preload of the Shadow Register, CC6xSR. The value is transferred to the actual Compare Register CC6xR with the T12 Shadow Transfer signal, T12_ST, that is assumed to be enabled.
Page 423 XC82x Capture/Compare Unit 6 (CCU6) Period Value = 5 T12 Count Zero Down Down CDIR Value n Value n+1 Value n+2 Value n+3 CC6x CC6x = 2 CC6x = 2 CC6x = 1 CC6x = 1 CC6x = 1 CC6x = 0...
Page 424 XC82x Capture/Compare Unit 6 (CCU6) Period Value CC61R CC62R T12 Count CC60R Zero Down Down Down CDIR Shadow Transfer CC60ST CC61ST CC62ST CCU6_MCT05518 Figure 20-14 Three-Channel Compare Waveforms User’s Manual 20-30 V1.0, 2010-02 CCU6, V4.0...
Page 425: Hysteresis-Like Control Mode
XC82x Capture/Compare Unit 6 (CCU6) 20.3.3.3 Hysteresis-Like Control Mode The hysteresis-like control mode (T12MSELL.MSEL6x = 1001 ) offers the possibility to switch off the PWM output if the input CCPOSx becomes 0 by clearing the State Bit CC6xST. This can be used as a simple motor control feature by using a comparator indicating, e.g., overcurrent.
Page 426: Compare Mode Output Path
XC82x Capture/Compare Unit 6 (CCU6) 20.3.4 Compare Mode Output Path Figure 20-15 gives an overview on the signal path from a channel State Bit to its output pin in its simplest form. As illustrated, a user has a variety of controls to determine the desired output signal switching behavior in relation to the current state of the State Bit, CC6xST.
Page 427 XC82x Capture/Compare Unit 6 (CCU6) contains a programmable Dead-Time Generation Block, that delays the passive to active edge of the switching signals by a programmable time (the active to passive edge is not delayed). The Dead-Time Generation Block, illustrated in...
Page 428: State Selection
XC82x Capture/Compare Unit 6 (CCU6) T12 Counter Value Compare Value active State Bit passive CC6xST active active Dead- passive passive Time CC6xST active with Dead- passive Time CC6xST active with Dead- passive Time CCU6_MCT05521 Figure 20-17 Dead-Time Generation Waveforms 20.3.4.2 State Selection...
Page 429: Output Modulation And Level Selection
XC82x Capture/Compare Unit 6 (CCU6) 20.3.4.3 Output Modulation and Level Selection The last block of the data path is the Output Modulation block. Here, all the modulation sources and the trap functionality are combined and control the actual level of the output pins (controlled by the modulation enable bits T1xMODENy and MCMEN in register MODCTRL, MODCTRH).
Page 430 XC82x Capture/Compare Unit 6 (CCU6) TRPS Trap Handling Block TRPEN0 CC63_O T13 Block Output active Level T13MODEN0 Modulation passive Selection CC60 CC60 CC60_O T12 Block + PSL0 COUT60_O Dead-Time T12MODEN0 MCMP0 Multi-Channel MCMP1 Mode MCMEN TRPEN1 Output active Level T13MODEN1...
Page 431 XC82x Capture/Compare Unit 6 (CCU6) 20.3.5 T12 Capture Modes Each of the three channels of the T12 Block can also be used to capture T12 time information in response to an external signal CC6xIN. In capture mode, the interrupt event CC6x_R is detected when a rising edge is detected at the input CC6xIN, whereas the interrupt event CC6x_F is detected when a falling edge is detected.
Page 432 XC82x Capture/Compare Unit 6 (CCU6) Capture Modes 2, 3 and 4 are shown in Figure 20-20. They differ only in the active edge causing the capture operation. In each of the three modes, when the selected edge is detected at the corresponding input signal CC6xIN, the current contents of the shadow register CC6xSR are transferred into register CC6xR, and the current Timer T12 contents are captured in register CC6xSR (simultaneous transfer).
Page 433 XC82x Capture/Compare Unit 6 (CCU6) Five further capture modes are called Multi-Input Capture Modes, as they use two different external inputs, signal CC6xIN and signal CCPOSx. Counter Register MSEL6x CC6xIN Edge Capture Mode Selection Detect State Bit Shadow Register Register CC6xR...
Page 434 XC82x Capture/Compare Unit 6 (CCU6) Table 20-9 Multi-Input Capture Modes Overview MSEL6x Mode Signal Active Edge T12 Stored in 1010 CC6xIN Rising CC6xR CCPOSx Falling CC6xSR 1011 CC6xIN Falling CC6xR CCPOSx Rising CC6xSR 1100 CC6xIN Rising CC6xR CCPOSx Rising CC6xSR...
Page 435: T12 Shadow Register Transfer
XC82x Capture/Compare Unit 6 (CCU6) 20.3.6 T12 Shadow Register Transfer A special shadow transfer signal (T12_ST) can be generated to facilitate updating the period and compare values of the compare channels CC60, CC61, and CC62 synchronously to the operation of T12. Providing a shadow register for values defining one PWM period facilitates a concurrent update by software for all relevant parameters.
Page 436: Timer T12 Operating Mode Selection
XC82x Capture/Compare Unit 6 (CCU6) A T12 shadow register transfer takes place (T12_ST active): • while timer T12 is not running (T12R = 0), or • STE12 = 1 and a Period-Match is detected while counting up, or • STE12 = 1 and a One-Match is detected while counting down When signal T12_ST is active, a shadow register transfer is triggered with the next cycle of the T12 clock.
Page 437 XC82x Capture/Compare Unit 6 (CCU6) 20.3.8 T12 related Registers 20.3.8.1 T12 Counter Register Register T12 represents the counting value of timer T12. It can only be written while the timer T12 is stopped. Write actions while T12 is running are not taken into account.
Page 438: Period Register
XC82x Capture/Compare Unit 6 (CCU6) 20.3.8.2 Period Register Register T12PRL/H contains the period value for timer T12. The period value is compared to the actual counter value of T12 and the resulting counter actions depend on the defined counting rules. This register has a shadow register and the shadow transfer is controlled by bit STE12.
Page 439 XC82x Capture/Compare Unit 6 (CCU6) Field Bits Type Description T12PVH [7:0] Timer T12 Period Value The value T12PVL defines the upper 8-bits of counter value for T12 leading to a period-match. When reaching this value, the timerT12 is set to zero (edge-aligned mode) or changes its count direction to down counting (center-aligned mode).
Page 440: Capture/Compare Registers
XC82x Capture/Compare Unit 6 (CCU6) 20.3.8.3 Capture/Compare Registers In compare mode, the registers CC6xRL/H (x = 0 - 2) are the actual compare registers for T12. The values stored in CC6xR are compared (all three channels in parallel) to the counter value of T12.
Page 441 XC82x Capture/Compare Unit 6 (CCU6) 20.3.8.4 Capture/Compare Shadow Registers The registers CC6xRL/H can only be read by SW, the modification of the value is done by a shadow register transfer from register CC6xSRL/H. The corresponding shadow registers CC6xSRL/H can be read and written by SW. In capture mode, the value of the T12 counter register can also be captured by registers CC6xSRL/H if the selected capture event is detected (depending on the selected capture mode).
Page 442 XC82x Capture/Compare Unit 6 (CCU6) Field Bits Type Description CCSH [7:0] Shadow Register for Channel x Capture/Compare Value In compare mode, the bit fields contents of CCS are transferred to the bit fields CCV for the corresponding channel during a shadow transfer. In capture mode, the captured value of T12 can be read from these registers.
Page 443: Dead-Time Control Register
XC82x Capture/Compare Unit 6 (CCU6) 20.3.8.5 Dead-time Control Register Register T12DTCL/H controls the dead-time generation for the timer T12 compare channels. Each channel can be independently enabled/disabled for dead-time generation. If enabled, the transition from passive state to active state is delayed by the value defined by bit field DTM.
Page 444 XC82x Capture/Compare Unit 6 (CCU6) Field Bits Type Description DTE2, Dead Time Enable Bits DTE1, Bits DTE0..DTE2 enable and disable the dead time DTE0 generation for each compare channel (0, 1, 2) of timer T12. Dead-Time Counter x is disabled. The...
Page 445 XC82x Capture/Compare Unit 6 (CCU6) 20.3.9 Capture/Compare Control Registers 20.3.9.1 Channel State Bits The Compare State Register CMPSTATL/H contains status bits monitoring the current capture and compare state and control bits defining the active/passive state of the compare channels. CMPSTATL...
Page 446 XC82x Capture/Compare Unit 6 (CCU6) 1) These bits are set and cleared according to the T12, T13 switching rules CMPSTATH Compare State Register High Reset Value: 00 RMAP: 0, PAGE: 3 COUT63P COUT62P COUT61P COUT60P T13IM CC62PS CC61PS CC60PS Field...
Page 447 XC82x Capture/Compare Unit 6 (CCU6) The Compare Status Modification Register CMPMODIFL/H provides software-control (independent set and clear conditions) for the channel state bits CC6xST. This feature enables the user to individually change the status of the output lines by software, for example when the corresponding compare timer is stopped.
Page 448 XC82x Capture/Compare Unit 6 (CCU6) CMPMODIFH Compare State Modification Register High Reset Value: 00 RMAP: 0, PAGE: 0 MCC63R MCC62R MCC61R MCC60R Field Bits Type Description MCC60R, Capture/Compare Status Modification Bits MCC61R, These bits are used to bits to set (MCC6xS...
Page 449 XC82x Capture/Compare Unit 6 (CCU6) 20.3.9.2 T12 Mode Control Register Register T12MSELL/H contains control bits to select the capture/compare functionality of the three channels of Timer T12. T12MSELL T12 Mode Select Register Low Reset Value: 00 RMAP: 0, PAGE: 2...
Page 450 XC82x Capture/Compare Unit 6 (CCU6) Field Bits Type Description HSYNC [6:4] Hall Synchronization Bit field HSYNC defines the source for the sampling of the Hall input pattern and the comparison to the current and the expected Hall pattern bit fields.
Page 451: Timer Control Registers
XC82x Capture/Compare Unit 6 (CCU6) 20.3.9.3 Timer Control Registers Register TCTR0L/H controls the basic functionality of both timers, T12 and T13. Note: A write action to the bit fields T12CLK or T12PRE is only taken into account while the timer T12 is not running (T12R=0). A write action to the bit fields T13CLK or T13PRE is only taken into account while the timer T13 is not running (T13R=0).
Page 452 XC82x Capture/Compare Unit 6 (CCU6) Field Bits Type Description T12R Timer T12 Run Bit T12R starts and stops timer T12. It is set/cleared by SW by setting bits T12RR or T12RS or it is cleared by HW according to the function defined by bit field T12SSC.
Page 453 XC82x Capture/Compare Unit 6 (CCU6) TCTR0H Timer Control Register 0 High Reset Value: 00 RMAP: 0, PAGE: 1 STE13 T13R T13PRE T13CLK Field Bits Type Description T13CLK [2:0] Timer T13 Input Clock Select Selects the input clock for timer T13 that is derived from the peripheral clock according to the equation <T13CLK>...
Page 454 XC82x Capture/Compare Unit 6 (CCU6) Field Bits Type Description STE13 Timer T13 Shadow Transfer Enable Bit STE13 enables or disables the shadow transfer of the T13 period value, the compare value and passive state select bit and level from their shadow registers to the actual registers if a T13 shadow transfer event is detected.
Page 455 XC82x Capture/Compare Unit 6 (CCU6) Register TCTR2L/H controls the single-shot and the synchronization functionality of both timers T12 and T13. Both timers can run in single-shot mode. In this mode they stop their counting sequence automatically after one counting period with a count value of zero.
Page 456 XC82x Capture/Compare Unit 6 (CCU6) Field Bits Type Description T13TEC [4:2] T13 Trigger Event Control bit field T13TEC selects the trigger event to start T13 (automatic set of T13R for synchronization to T12 compare signals) according to following combinations: no action...
Page 457 XC82x Capture/Compare Unit 6 (CCU6) TCTR2H Timer Control Register 2 High Reset Value: 00 RMAP: 0, PAGE: 2 T13RSEL T12RSEL Field Bits Type Description T12RSEL [1:0] Timer T12 External Run Selection Bit field T12RSEL defines the event of signal T12HR that can set the run bit T12R by HW.
Page 458 XC82x Capture/Compare Unit 6 (CCU6) Register TCTR4L/H provides software-control (independent set and clear conditions) for the run bits T12R and T13R. Furthermore, the timers can be reset (while running) and bits STE12 and STE13 can be controlled by software. Reading these bits always returns...
Page 459 XC82x Capture/Compare Unit 6 (CCU6) Field Bits Type Description [5:4] reserved; returns 0 if read; should be written with 0; Note: A simultaneous write of a 1 to bits that set and clear the same bit will trigger no action. The corresponding bit will remain unchanged.
Page 460 XC82x Capture/Compare Unit 6 (CCU6) Field Bits Type Description [5:3] reserved; returns 0 if read; should be written with 0; Note: A simultaneous write of a 1 to bits that set and clear the same bit will trigger no action. The corresponding bit will remain unchanged.
Page 461 XC82x Capture/Compare Unit 6 (CCU6) 20.4 Operating Timer T13 Timer T13 is implemented similarly to Timer T12, but only with one channel in compare mode. A 16-bit up-counter is connected to a channel register via a comparator, that generates a signal when the counter contents match the contents of the channel register.
Page 462 XC82x Capture/Compare Unit 6 (CCU6) on the associated control bit STE13. Providing a shadow register for the period value as well as for other values related to the generation of the PWM signal facilitates a concurrent update by software for all relevant parameters (refer to Table 20.4.5).
Page 463 XC82x Capture/Compare Unit 6 (CCU6) timings to T12 events, e.g. to generate a programmable delay via T13 after an edge of a T12 compare channel before triggering an AD conversion (T13 can trigger ADC conversions). Timer T13 can be cleared to 0000 via control bit T13RES.
Page 464: T13 Counting Scheme
XC82x Capture/Compare Unit 6 (CCU6) 20.4.2 T13 Counting Scheme This section describes the clocking and the counting capabilities of T13. 20.4.2.1 T13 Counting The period of the timer is determined by the value in the period Register T13PR according to the following formula: = <Period-Value>...
Page 465 XC82x Capture/Compare Unit 6 (CCU6) 20.4.2.2 Single-Shot Mode In Single-Shot Mode, the timer run bit T13R is cleared by hardware. If bit T13SSC = 1, the timer T13 will stop when the current timer period is finished. Period Value Compare...
Page 466 XC82x Capture/Compare Unit 6 (CCU6) 20.4.2.3 Synchronization to T12 Timer T13 can be synchronized to a T12 event. Bit fields T13TEC and T13TED select the event that is used to start Timer T13. The selected event sets bit T13R via HW, and T13 starts counting.
Page 467 XC82x Capture/Compare Unit 6 (CCU6) Table 20-11 T12 Trigger Event Selection T13TEC Selected Event None T12 Compare Event on Channel 0 (CM_CC60) T12 Compare Event on Channel 1 (CM_CC61) T12 Compare Event on Channel 2 (CM_CC62) T12 Compare Event on any Channel (0, 1, 2)
Page 468: T13 Compare Mode
XC82x Capture/Compare Unit 6 (CCU6) 20.4.3 T13 Compare Mode Associated with Timer T13 is one compare channel, that can perform compare operations with regard to the contents of the T13 counter. Figure 20-23 gives an overview on the T13 channel in Compare Mode. The channel is...
Page 469 XC82x Capture/Compare Unit 6 (CCU6) CM_63. In addition, the state bit can be set or cleared by software via bits MCC63S and MCC63R in register CMPMODIFL, CMPMODIFH. A modification of the State Bit CC63ST by hardware is only possible while Timer T13 is running (T13R = 1).
Page 470 XC82x Capture/Compare Unit 6 (CCU6) 20.4.4 Compare Mode Output Path Figure 20-30 gives an overview on the signal path from the channel State Bit CC63ST to its output pin COUT63. As illustrated, a user can determine the desired output behavior in relation to the current state of CC63ST. Please refer to Section 20.3.4.3...
Page 471: T13 Shadow Register Transfer
XC82x Capture/Compare Unit 6 (CCU6) state, the level specified directly by PSL63 is output. If it is in the active state, the inverted level of PSL63 is output. This allows the user to adapt the polarity of an active output signal to the connected circuitry.
Page 472 XC82x Capture/Compare Unit 6 (CCU6) Read Read Read Read Period Register PSL63 CC63PS T13IM T13PR Period Shadow PSL63 CC63PS T13IM Register T13PR Shadow Shadow Shadow Write Write Write Write Read Compare Register CC63R T13_ST Compare Shadow Register CC63SR Write Read...
Page 473 XC82x Capture/Compare Unit 6 (CCU6) 20.4.6 T13 related Registers 20.4.6.1 T13 Counter Register The generation of the patterns for a single channel pulse width modulation (PWM) is based on timer T13. The registers related to timer T13 can be concurrently updated (with well-defined conditions) in order to ensure consistency of the PWM signal.
Page 474 XC82x Capture/Compare Unit 6 (CCU6) Field Bits Type Description T13CVH [7:0] Timer 13 Counter Value This register represents the upper 8-bits of 16-bit counter value of Timer13. Note: While timer T13 is stopped, the internal clock divider is reset in order to ensure reproducible timings and delays.
Page 475: Type Description
XC82x Capture/Compare Unit 6 (CCU6) 20.4.6.2 Period Register The generation of the patterns for a single channel pulse width modulation (PWM) is based on timer T13. The registers related to timer T13 can be concurrently updated (with well-defined conditions) in order to ensure consistency of the PWM signal. T13 can be synchronized to several timer T12 events.
Page 476 XC82x Capture/Compare Unit 6 (CCU6) Field Bits Type Description T13PVH [7:0] T13 Period Value The value T13PV defines the upper 8-bits of counter value for T13 leading to a period-match. When reaching this value, the timer T13 is set to zero.
Page 477: Compare Shadow Register
XC82x Capture/Compare Unit 6 (CCU6) 20.4.6.3 Compare Register Registers CC63RL/H is the actual compare register for T13. The values stored in CC63RL/H is compared to the counter value of T13. The State Bit CC63ST is located in register CMPSTATL. CC63RL...
Page 478 XC82x Capture/Compare Unit 6 (CCU6) CC63SRL Compare Shadow Register for T13 Low Reset Value: 00 RMAP: 0, PAGE: 0 CCSL Field Bits Type Description CCSL [7:0] Shadow Register for Channel CC63 Compare Value The bit field contents of CCSL is transferred to the lower 8-bits of bit field CCV during a shadow transfer.
Page 479: Trap Handling
XC82x Capture/Compare Unit 6 (CCU6) 20.5 Trap Handling The trap functionality permits the PWM outputs to react on the state of the input signal CTRAP. This functionality can be used to switch off the power devices if the trap input becomes active (e.g.
Page 480 XC82x Capture/Compare Unit 6 (CCU6) Clearing of TRPF is controlled by the mode control bit TRPM2. If TRPM2 = 0, TRPF is automatically cleared by HW when CTRAP returns to the inactive level (CTRAP = 1) or if the trap input is disabled (TRPPEN = 0). When TRPM2 = 1, TRPF must be reset by SW after CTRAP has become inactive.
Page 481: Multi-Channel Mode
XC82x Capture/Compare Unit 6 (CCU6) 20.6 Multi-Channel Mode The Multi-Channel mode offers the possibility to modulate all six T12-related output signals with one instruction. The bits in bit field MCMOUTL.MCMP are used to specify the outputs that may become active. If Multi-Channel mode is enabled (bit MODCTRL.MCMEN = 1), only those outputs may become active, that have a 1 at the...
Page 482 XC82x Capture/Compare Unit 6 (CCU6) (the event is not necessarily synchronous to the modulating PWM), and is cleared when the transfer takes place. This flag can be monitored by software to check for the status of this logic block. If the shadow transfer from MCMPS to MCMP takes place, bit ISH.STR becomes set and an interrupt can be generated.
Page 483 XC82x Capture/Compare Unit 6 (CCU6) Table 20-14 Multi-Channel Mode Switching Synchronization (cont’d) SWSYN Synchronization Event (see register MCMCTR) T12 Zero-Match (T12_ZM), the MCM shadow transfer is synchronized to a T12 PWM Reserved, no action User’s Manual 20-89 V1.0, 2010-02 CCU6, V4.0...
Page 484: Hall Sensor Mode
XC82x Capture/Compare Unit 6 (CCU6) 20.7 Hall Sensor Mode For Brushless DC-Motors in block commutation mode, the Multi-Channel Mode has been introduced to provide efficient means for switching pattern generation. These patterns need to be output in relation to the angular position of the motor. For this, usually Hall sensors or Back-EMF sensing are used to determine the angular rotor position.
Page 485: Hall Pattern Evaluation
XC82x Capture/Compare Unit 6 (CCU6) 20.7.1 Hall Pattern Evaluation The Hall sensor inputs CCPOSx can be permanently monitored via an edge detection block (with the module clock ). In order to suppress spikes on the Hall inputs due to noise in rugged inverter environment, two optional noise filtering methods are supported by the Hall logic (both methods can be combined).
Page 486 XC82x Capture/Compare Unit 6 (CCU6) Figure 20-36 illustrates the events for Hall pattern evaluation and the noise filter logic, Table 20-15 summarizes the selectable trigger input signals. Table 20-15 Hall Sensor Mode Trigger Event Selection HSYNC Selected Event (see register T12MSELL, T12MSELH) Any edge at any of the inputs CCPOSx, independent from any PWM signal (permanent check).
Page 487: Hall Pattern Compare Logic
XC82x Capture/Compare Unit 6 (CCU6) 20.7.2 Hall Pattern Compare Logic Figure 20-37 gives an overview on the double-register structure and the pattern compare logic. Software writes the next modulation pattern (MCMPS) and the corresponding current (CURHS) and expected (EXPHS) Hall patterns into the shadow register MCMOUTS.
Page 488 XC82x Capture/Compare Unit 6 (CCU6) At every correct Hall event (CM_CHE), the next Hall patterns are transferred from the shadow register MCMOUTS into MCMOUT (Hall pattern shadow transfer HP_ST), and a new Hall pattern with its corresponding output pattern can be loaded (e.g. from a predefined table in memory) by software into MCMOUTS.
Page 489 XC82x Capture/Compare Unit 6 (CCU6) Clear RCHE INPCHE To SR0 >1 SCHE To SR1 To SR2 CM_CHE To SR3 ENCHE Hall Compare Clear RWHE INPERR Logic To SR0 >1 SWHE To SR1 CM_WHE To SR2 To SR3 ENWHE ENIDLE >1...
Page 490: Hall Mode For Brushless Dc-Motor Control
XC82x Capture/Compare Unit 6 (CCU6) 20.7.4 Hall Mode for Brushless DC-Motor Control The CCU6 provides a mode for the Timer T12 Block especially targeted for convenient control of block commutation patterns for Brushless DC-Motors. This mode is selected by setting all T12MSELL/T12MSELH.MSEL6x bit fields of the three T12 Channels to...
Page 491 XC82x Capture/Compare Unit 6 (CCU6) CC62 Compare Hall Event captures for Time-Out and resets T12 CC62 Comp. T12 Count CC61 Compare for Phase Delay CC61 Comp. 0000 CCPOS0 CCPOS1 CCPOS2 = 101 = 001 = 011 = 010 = 110...
Page 492 XC82x Capture/Compare Unit 6 (CCU6) 20.8 Modulation Control Registers 20.8.1 Modulation Control This register contains bits enabling the modulation of the corresponding output signal by PWM pattern generated by the timers T12 and T13. Furthermore, the multi-channel mode can be enabled as additional modulation source for the output signals.
Page 493: Type Description
XC82x Capture/Compare Unit 6 (CCU6) MODCTRH Modulation Control Register High Reset Value: 00 RMAP: 0, PAGE: 2 ECT13O T13MODEN Field Bits Type Description T13MODEN [5:0] T13 Modulation Enable These bits enable the modulation of the corresponding output signal by the PWM pattern CC63_O generated by timer T13.
Page 494 XC82x Capture/Compare Unit 6 (CCU6) 20.8.2 Trap Control Register The register TRPCTRL/H controls the trap functionality. It contains independent enable bits for each output signal and control bits to select the behavior in case of a trap condition. The trap condition is a low level on the CTRAP input pin, that is monitored (inverted level) by bit ISH.TRPF.
Page 495 XC82x Capture/Compare Unit 6 (CCU6) Field Bits Type Description TRPM2 Trap Mode Control Bit 2 This bit defines how the trap flag TRPF can be cleared after the trap input condition (CTRAP = 0 and TRPPEN = 1) is no longer valid (either by CTRAP = 1 or by TRPPEN = 0).
Page 496 XC82x Capture/Compare Unit 6 (CCU6) Field Bits Type Description TRPEN [5:0] Trap Enable Control Setting a bit enables the trap functionality for the following corresponding output signals: TRPEN0 = TRPCTR.8 for output CC60 TRPEN1 = TRPCTR.9 for output COUT60 TRPEN2 = TRPCTR.10 for output CC61 TRPEN3 = TRPCTR.11 for output COUT61...
Page 497: Passive State Level Register
XC82x Capture/Compare Unit 6 (CCU6) 20.8.3 Passive State Level Register Register PSLR defines the passive state level of the PWM outputs of the module. The passive state level is the value that is driven during the passive state of the output.
Page 498 XC82x Capture/Compare Unit 6 (CCU6) 20.8.4 Multi-Channel Mode Registers Register MCMCTR contains control bits for the multi-channel functionality. MCMCTR Multi-Channel Mode Control Register (A7 Reset Value: 00 RMAP: 0, PAGE: 2 SWSYN SWSEL Field Bits Type Description SWSEL [2:0] Switching Selection...
Page 499 XC82x Capture/Compare Unit 6 (CCU6) Field Bits Type Description SWSYN [5:4] Switching Synchronization Bit field SWSYN defines the synchronization mechanism of the shadow transfer event MCM_ST if it has been requested before (flag R set by an event selected by SWSEL) and if MCMEN = 1. This...
Page 500 XC82x Capture/Compare Unit 6 (CCU6) Register MCMOUTSL/H contains bits used as pattern input for the multi-channel mode and the Hall mode. This register is a shadow register (that can be read and written) for register MCMOUT, indicating the currently active signals.
Page 501 XC82x Capture/Compare Unit 6 (CCU6) Field Bits Type Description EXPHS [2:0] Expected Hall Pattern Shadow Bit field EXPHS is the shadow bit field for bit field EXPH. The shadow transfer takes place when a correct Hall event is detected (CM_CHE).
Page 502 XC82x Capture/Compare Unit 6 (CCU6) Field Bits Type Description MCMP [5:0] Multi-Channel PWM Pattern Bit field MCMP defines the output pattern for the multi-channel mode. If this mode is enabled by MODCTR.MCMEN = 1, the output state of all T12 related PWM outputs can be modified.
Page 503 XC82x Capture/Compare Unit 6 (CCU6) MCMOUTH Multi-Channel Mode Output Register High Reset Value: 00 RMAP: 0, PAGE: 3 CURH EXPH Field Bits Type Description EXPH [10:8] Expected Hall Pattern Bit field EXPH is updated by a shadow transfer HP_ST from bit field EXPHS.
Page 504 XC82x Capture/Compare Unit 6 (CCU6) 20.9 Interrupt Handling This section describes the interrupt handling of the CCU6 module. 20.9.1 Interrupt Structure The HW interrupt event or the SW setting of the corresponding interrupt set bit (in register ISS) sets the event indication flags (in register IS) and can trigger the interrupt generation.
Page 505 XC82x Capture/Compare Unit 6 (CCU6) T12_PM Interrupt Request T12 Counter Reg. CC6x_0IC T12_OM Interrupt Request CDIR Reg. CC6x_1IC CC6x_R T12 Capture Interrupt Request Compare Reg. CC6x_2IC CC6x_F Channels CC6x Interrupt Request Reg. CC6x_3IC T13_PM T13 Counter Interrupt Interrupt Set Control Logic...
Page 506 XC82x Capture/Compare Unit 6 (CCU6) 20.9.2 Interrupt Registers 20.9.2.1 Interrupt Status Register Register ISL/H contains the individual interrupt request bits. This register can only be read, write actions have no impact on the contents of this register. The SW can set or clear the bits individually by writing to the registers ISSL/H (to set the bits) or to register ISRL/H (to clear the bits).
Page 507 XC82x Capture/Compare Unit 6 (CCU6) Field Bits Type Description ICC60F, Capture, Compare-Match Falling Edge Flag ICC61F, This bit indicates that event CC6x_F has been ICC62F detected. This event occurs in compare mode when a compare-match is detected while T12 is counting...
Page 508 XC82x Capture/Compare Unit 6 (CCU6) Field Bits Type Description T13PM Timer T13 Period-Match Flag This bit indicates that a timer T13 period-match (T13_PM) has been detected. The event has not yet been detected. The event has been detected. TRPF Trap Flag This bit indicates if a trap condition (input CTRAP = 0 or by SW) is / has been detected.
Page 509 XC82x Capture/Compare Unit 6 (CCU6) Field Bits Type Description Multi-Channel Mode Shadow Transfer Request This bit indicates that a shadow transfer from MCMPS to MCMP (MCM_ST) has taken place. The event has not yet been detected. The event has been detected.
Page 510 XC82x Capture/Compare Unit 6 (CCU6) 20.9.2.2 Interrupt Status Set Register Register ISSL/H contains individual interrupt request set bits to generate a CCU6 interrupt request by software. Writing a 1 sets the bit(s) in register ISL/H at the corresponding bit position(s) and can generate an interrupt event (if available and enabled).
Page 511 XC82x Capture/Compare Unit 6 (CCU6) Field Bits Type Description ST13CM Set Timer T13 Compare-Match Flag No action Bit T13CM will be set. ST13PM Set Timer T13 Period-Match Flag No action Bit T13PM will be set. STRPF Set Trap Flag No action Bits TRPF and TRPS will be set.
Page 512 XC82x Capture/Compare Unit 6 (CCU6) 20.9.2.3 Status Reset Register Register ISRL/H contains bits to individually clear the interrupt event flags by software. Writing a 1 clears the bit(s) in register IS at the corresponding bit position(s). All bit positions read as 0.
Page 513 XC82x Capture/Compare Unit 6 (CCU6) Field Bits Type Description RT13CM Reset Timer T13 Compare-Match Flag No action Bit T13CM will be cleared. RT13PM Reset Timer T13 Period-Match Flag No action Bit T13PM will be cleared. RTRPF Reset Trap Flag No action...
Page 514: Interrupt Enable Register
XC82x Capture/Compare Unit 6 (CCU6) 20.9.2.4 Interrupt Enable Register Register IENL/H contains the interrupt enable bits and a control bit to enable the automatic idle function in the case of a wrong hall pattern. IENL Interrupt Enable Register Low Reset Value: 00...
Page 515 XC82x Capture/Compare Unit 6 (CCU6) Field Bits Type Description ENT12PM Enable Interrupt for T12 Period-Match No interrupt will be generated if the set condition for bit T12PM in register IS occurs. An interrupt will be generated if the set condition for bit T12PM in register IS occurs.
Page 516 XC82x Capture/Compare Unit 6 (CCU6) Field Bits Type Description ENTRPF Enable Interrupt for Trap Flag No interrupt will be generated if the set condition for bit TRPF in register IS occurs. An interrupt will be generated if the set condition for bit TRPF in register IS occurs.
Page 517 XC82x Capture/Compare Unit 6 (CCU6) Field Bits Type Description reserved; returns 0 if read; should be written with 0; User’s Manual 20-123 V1.0, 2010-02 CCU6, V4.0...
Page 518 XC82x Capture/Compare Unit 6 (CCU6) 20.9.2.5 Interrupt Node Pointer Register Register INPL/H contains the interrupt node pointers allowing a flexible interrupt handling. These bit fields define which service request output will be activated if the corresponding interrupt event occurs and the interrupt generation for this event is enabled.
Page 519 XC82x Capture/Compare Unit 6 (CCU6) INPH Interrupt Node Pointer Register High (9F Reset Value: 39 RMAP: 0, PAGE: 2 INPT13 INPT12 INPERR Field Bits Type Description INPERR [1:0] Interrupt Node Pointer for Error Interrupts This bit field defines the service request output...
Page 520: Input Selection
XC82x Capture/Compare Unit 6 (CCU6) 20.10 General Module Operation This section provides information about the: • Input selection (see Section 20.10.1) • General register description (see Section 20.10.2) 20.10.1 Input Selection Each CCU6 input signal can be selected from a vector of four or eight possible inputs by...
Page 521: General Registers
XC82x Capture/Compare Unit 6 (CCU6) 20.10.2 General Registers 20.10.2.1 Port Input Select Registers Registers PISEL0L and PISEL0H contain bit fields selecting the actual input signal for the module inputs. PISEL0L Port Input Select Register Low Reset Value: 00 RMAP: 0, PAGE: 3...
Page 522 P1 overcurrent detection output is selected. Any input source from above option 00 or 01 is selected to trigger a CTRAP. ADC channel event is selected. 1) Applicable for XC83x only. Unused for XC82x. PISEL0H Port Input Select Register 0 High Reset Value: 00...
Page 523 XC82x Capture/Compare Unit 6 (CCU6) Field Bits Type Description ISPOS1 [3:2] Input Select for CCPOS1 This bit field defines the input signal used as CCPOS1 input. Input pin for CCPOS1_0. Input pin for CCPOS1_1. Unused. ADC channel 1 boundary limit check event.
Page 524 XC82x Capture/Compare Unit 6 (CCU6) Field Bits Type Description IST13HR [1:0] Input Select for T13HR This bit field defines the input signal used as T13HR input. Any of the input pin for T13HR[7:0] CCU6 SR2 output. CCU6 SR3 output. ADC channel event.
Page 525: Register Mapping
XC82x Capture/Compare Unit 6 (CCU6) 20.11 Register Mapping The addresses of the kernel SFRs are listed in Table 20-16. Table 20-16 SFR Address List for Pages 0 – 3 Address Page 0 Page 1 Page 2 Page 3 CC63SRL CC63RL...
Page 526: Analog To Digital Converter
XC82x Analog to Digital Converter Analog to Digital Converter The Analog to Digital Converter module (ADC) of the XC82x uses the successive approximation method to convert analog input values (voltages) to discrete digital values. One ADC kernel (ADC0) operate on a user-selectable number of input channels.
Page 527 XC82x Analog to Digital Converter The following features describe the functionality of an ADC kernel: • Input voltage range from 0 V up to analog supply voltage ( = 3.0 V to 5.5 V) • Three internal reference voltage source selectable for each channel to support ratiometric measurements and different signal scales, which are: –...
Page 528 XC82x Analog to Digital Converter 21.1 System Information This section provides system information relevant to the ADC. 21.1.1 Pinning The ADC pin assignment for XC82x is shown in Table 21-1. Table 21-1 ADC Pin Functions and Selection Function Desciption Selected By P2.0...
Page 529 XC82x Analog to Digital Converter 21.1.3 Interrupt Events and Assignment Table 21-2 lists the interrupt event sources from the ADC, and the corresponding event interrupt enable bit and flag bit. Table 21-2 ADC Interrupt Events Event Event Interrupt Enable Bit Event Flag Bit...
Page 530 XC82x Analog to Digital Converter Table 21-4 ADC Output Interconnections ADC Function/Signal Connected Other Selected By Module Inputs Channel Events ADC channel event (o): CCU6 input (i): T12HR CCU6_PISEL0H.IST12HR = 11 ADC_CHEV CCU6 input (i): T13HR CCU6_PISEL2.IST13HR = 11 ADC channel event 0 (o): CCU6 input (i): CTRAP CCU6_PISEL0L.ISTRP = 11...
Page 531 XC82x Analog to Digital Converter Table 21-5 ADC Input Interconnection ADC Function/Signal Connected Other Module Function/Signal Request Source x (x = 0,1) Request Source x Trigger 0 Input (i): CCU6 service request output SR2 (o): REQTRxA CCU6_SR2 Request Source x Trigger 1 Input (i):...
Page 532 XC82x Analog to Digital Converter 21.2 Introduction and Basic Structure A set of functional units can be configured according to the requirements of a given application. These units build a path from the input signals to the digital results. Vddp 1.2 VREF...
Page 533 XC82x Analog to Digital Converter Input Channel Selection The analog input multiplexer selects one of up to 8 analog inputs (CH0 - CH7) to be converted. Two sources can select a linear sequence or an arbitrary sequence. The priorities of these sources can be configured.
Page 534 XC82x Analog to Digital Converter • Result events indicate the availability of new result data in the corresponding result register. If data reduction or digital low pass filter mode is active, events are generated only after a complete accumulation sequence.
Page 535: Electrical Models
During the conversion phase the stored voltage is converted to a digital result. The reference voltage path is a simplified model for this. Input Signal Path The ADC of the XC82x uses a switched capacitor field represented by (small parasitic capacitances are present at each input pin). During the sample phase, the...
Page 536 XC82x Analog to Digital Converter to be actually converted does not immediately follow V . The value R of the analog voltage source and the desired precision of the conversion strongly define the required length of the sample phase. To reduce the influence of R...
Page 537: Transfer Characteristics And Error Definitions
XC82x Analog to Digital Converter 21.4 Transfer Characteristics and Error Definitions The transfer characteristic of the ADC describes the association of analog input voltages to the 2 discrete digital result values (n bits resolution). Each digital result value (in the...
Page 538 The different parts of an ADC kernel are driven by clock signals that are based on the clock of the bus that is used to access the ADC module. The ADC in the XC82x device are connected to the system clock, so •...
Page 539: Type Description
XC82x Analog to Digital Converter Note: If the clock generation for the converter of the ADC falls below a minimum value or is stopped during a running conversion, the conversion result can be corrupted. For correct ADC results, the frequency of must not exceed the defined range.
Page 540 XC82x Analog to Digital Converter Field Bits Type Description [5:4] Conversion Time Control This bit field defines the divider ratio for the divider stage of the internal analog clock . This clock ADCI provides the internal time base for the conversion and sample time calculations.
Page 541 XC82x Analog to Digital Converter Field Bits Type Description BUSY Analog Part Busy This bit indicates that a conversion is currently active. The analog part is idle. A conversion is currently active. SAMPLE Sample Phase This bit indicates that an analog input signal is currently sampled.
Page 542 XC82x Analog to Digital Converter 21.6 Conversion Request Generation The conversion request unit of each ADC kernel autonomously handles the generation of conversion requests. Two request sources can generate requests for the conversion of an analog channel. The arbiter resolves concurrent requests and selects the channel to be converted next.
Page 543 XC82x Analog to Digital Converter Two types of requests sources are available: • A channel scan source can issue conversion requests for a coherent sequence of input channels. This sequence begins with the highest enabled channel number and continues towards lower channel numbers. Up to channels can be enabled for the scan sequence.
Page 544 XC82x Analog to Digital Converter 21.6.1 Channel Scan Request Source Handling Each analog input channel can be included in or excluded from the scan sequence (see bits in register ADC_CRCR1). The programmed register value remains unchanged by an ongoing scan sequence. The scan sequence starts with the highest enabled channel number and continues towards lower channel numbers.
Page 545 XC82x Analog to Digital Converter Scan Source Operation Configure the scan request source by executing the following actions: • Select the input channels for the sequence by programming ADC_CRCR1 • If hardware trigger is desired, select the appropriate trigger inputs by programming ADC_ETRCR.
Page 546 XC82x Analog to Digital Converter Scan Request Source Events and Interrupts A request source event of a scan source occurs if the last conversion of a scan sequence is finished (all pending bits = 0). A request source event interrupt can be generated...
Page 547 XC82x Analog to Digital Converter Field Bits Type Description ENTR Enable External Trigger This bit enables the external trigger possibility. If enabled, the load event takes place if a rising edge is detected at the external trigger input REQTR. The external trigger is disabled.
Page 548 XC82x Analog to Digital Converter The Conversion Request 1 Control Register selects the channels to be converted by request source 1 (channel scan source). Its bits are used to update the pending register CRPR1, when the load event occurs. Note: Writes to register CRPR1 also update CRCR1 and generate a load event.
Page 549 XC82x Analog to Digital Converter The Conversion Request Pending Register indicates which channels of request source 1 (channel scan source) are requesting a conversion. Its bits are updated from pending register CRCR1, when the load event occurs. Note: Writes to register CRPR1 also update CRCR1 and generate a load event.
Page 550 XC82x Analog to Digital Converter CRCR1 (that is why they are marked ‘rwh’) and leads to a load event one clock cycle later. 21.6.2 Queued Request Source Handling A queued request source supports short conversion sequences of arbitrary channels (contrary to a scan request source with a fixed conversion order for the enabled channels).
Page 551 Properties of the Queued Request Source The ADC kernels of the XC82x provide one queued request source with buffer size: • Queued request source 0 provides 4 buffer stages and can handle sequences of up to 4 input channel entries.
Page 552 XC82x Analog to Digital Converter Queued Source Operation Configure the queued request source by executing the following actions: • Define the sequence by writing the entries to the queue input ADC_QINR0. Initialize the complete sequence before enabling the request source, because with enabled refill feature, software writes to QINRx are not allowed.
Page 553 XC82x Analog to Digital Converter Queue Request Source Events and Interrupts A request source event of a queued source occurs when a conversion is finished. A request source event interrupt can be generated based on a request source event according to the structure shown in Figure 21-9.
Page 554 XC82x Analog to Digital Converter The Queue Mode Register configures the operating mode of a queued request source. ADC_QMR0 Queue Mode Register Reset Value: 00 RMAP: 0, PAGE: 6 TREV FLUSH CLRV ENTR ENGT Field Bits Type Description ENGT Enable Gate This bit enables the gating functionality for the request source.
Page 555 XC82x Analog to Digital Converter Field Bits Type Description Clear Event Bit No action Bit EV is cleared. 1, 3 Reserved Returns 0 if read; should be written with 0. Note: Before SW modifies the queue content by QMR.CLRV or QMR.FLUSH, all HW actions related to this queue have to be finished.
Page 556 XC82x Analog to Digital Converter The Queue Status Register indicates the current status of the queued source. The filling level and the empty information refer to the queue intermediate stages (if available) and to the queue register 0. An aborted conversion stored in the backup stage is not indicated by these bits (therefore, see QBURx.V).
Page 557 XC82x Analog to Digital Converter Field Bits Type Description EMPTY Queue Empty This bit indicates if the sequential source contains valid entries. A new entry is ignored if the queue is filled (EMPTY = 0). The queue is filled with 'FILL+1' valid entries in the queue.
Page 558 XC82x Analog to Digital Converter The Queue Input Register is the entry point for conversion requests of a queued request source. ADC_QINR0 Queue Input Register 0 Reset Value: 00 RMAP: 0, PAGE: 6 EXTR ENSI REQCHNR Field Bits Type Description...
Page 559 XC82x Analog to Digital Converter The queue registers 0 monitor the status of the pending request (queue stage 0). ADC_Q0R0 Queue 0 Register 0 Reset Value: 00 RMAP: 0, PAGE: 6 EXTR ENSI REQCHNR Field Bits Type Description REQCHNR [2:0]...
Page 560 XC82x Analog to Digital Converter Field Bits Type Description ENSI Enable Source Interrupt This bit indicates if a source interrupt will be generated when the conversion is completed. The interrupt trigger becomes activated if the conversion requested by the source has been completed and ENSI = 1.
Page 561 XC82x Analog to Digital Converter The Queue Backup Registers monitor the status of an aborted queued request. ADC_QBUR0 Queue Backup Register 0 Reset Value: 00 RMAP: 0, PAGE: 6 EXTR ENSI REQCHNR Field Bits Type Description REQCHNR [2:0] Request Channel Number This bit field is updated by bit field Q0R0.REQCHNR...
Page 562 XC82x Analog to Digital Converter Note: Registers QBURx share addresses with registers QINRx. Read operations return the status bits from register QBURx. Write operations target the control bits in register QINRx. 21.6.3 Hardware Trigger Selection Each request source can be activated either by software or by a hardware trigger signal.
Page 563 Additional arbitration slots can be inserted to adjust the timing to other products (not required for the XC82x). At the end of each arbitration round, the arbiter has determined the highest priority conversion request.
Page 564 XC82x Analog to Digital Converter User’s Manual 21-39 V1.0, 2010-02 ADC, V2.1...
Page 565 XC82x Analog to Digital Converter 21.7.1 Arbiter Timing The timing of the arbiter (i.e. of an arbitration round) is determined by the number of arbitration slots within an arbitration round and by the duration of an arbitration slot. An arbitration round consist of 4arbitration slots...
Page 566 XC82x Analog to Digital Converter 21.7.2 Request Source Priority and Conversion Start Mode Each request source has a configurable priority, so the arbiter can resolve concurrent conversion requests from different sources. The request with the highest priority is selected for conversion. These priorities can be adapted to the requirements of a given application (see register ADC_PRAR).
Page 567 XC82x Analog to Digital Converter Field Bits Type Description CSM1 Conversion Start Mode of Request Source 1 This bit defines the conversion start mode of the parallel request source 1. The wait-for-start mode is selected. The cancel-inject-repeat mode is selected.
Page 568 XC82x Analog to Digital Converter Conversion Start Mode When the arbiter has selected the request to be converted next, the handling of this channel depends on the current activity of the converter: • Converter is currently idle: the conversion of the arbitration winner is started immediately.
Page 569 XC82x Analog to Digital Converter request channel B request channel A conversions w ait-for-start mode cancel-inject-repeat mode ADC_conv _ starts Figure 21-11 Conversion Start Modes The conversion start mode can be individually programmed for each request source by bits in register ADC_PRAR and is applied to all channels requested by the source.
Page 570: Analog Input Channel Configuration
XC82x Analog to Digital Converter 21.8 Analog Input Channel Configuration For each analog input channel, a number of parameters can be configured that control the conversion of this channel. After a channel has won the arbitration, its parameters are applied to the converter. The channel control registers (CHCTRx on...
Page 571 XC82x Analog to Digital Converter AD C kernel Vddp va_ref va_gnd Vssp AIN CH0 result AIN CH1 handling converter conversion AIN CH3/7 request control control Interrupt generation ADC_single _ended_measurement2.vsd Figure 21-12 Single ended measurement with Vddp, Vssp In differential like ADC conversion with internal 1.2V voltage reference and ground reference taken from CH0.
Page 572 XC82x Analog to Digital Converter ADC kernel 1.2VREF va_altref va_altgnd Vssp AIN CH0 result AIN CH1 handling converter conversion AIN CH3/7 request control control Interrupt generation ADC_single _ended_1.2Vref_vssp _measurement2.vsd Figure 21-14 Single ended measurement with internal 1.2V voltage reference and Vssp.
Page 573 XC82x Analog to Digital Converter 21.8.2 Channel Parameters Each analog input channel is configured by its associated channel control register. The sample time and the result width are selected via an input class. The Channel Control Registers select the control parameters for each input channel, it contain bits to select the targetted result register, selection of internal reference voltages, controls the limit check mechanism and boundary flags.
Page 574 XC82x Analog to Digital Converter Field Bits Type Description [6:4] Limit Check Control This bit field defines the behavior of the limit checking mechanism. See Section 21.8.3 Never Result outside area I Result outside area II Result outside area III...
Page 575 XC82x Analog to Digital Converter Field Bits Type Description RESRSEL [1:0] Result Register Selection This bit field defines which result register will be the target of a conversion of this channel. The result register 0 is selected. The result register 1 is selected.
Page 576 XC82x Analog to Digital Converter An input class defines the length of the sample phase and the resolution of the conversion. The default settings select the minimum sample phase length of 2 cycles. ADCI The Input Class Registers select the sample time and the resolution for each input class.
Page 577: Limit Checking
XC82x Analog to Digital Converter 21.8.3 Limit Checking The limit checking mechanism automatically compares each conversion result to two boundary values (boundary A and boundary B). For each channel, the user can select these boundaries from a set of 2 programmable values (ADC_LCBR0 to ADC_LCBR1).
Page 578 Note: In the case of an over-current protection, the channel event can be used to disable PWM generation to reduce the current (in the XC82x, an interrupt output line of the ADC module is connected to a corresponding input of the CCU6x units to allow fast reactions without CPU intervention).
Page 579: Alias Feature
XC82x Analog to Digital Converter The Limit Check Boundary Registers define compare values (boundaries) for the limit checking unit. ADC_LCBR0 Limit Check Boundary Register 0 Reset Value: 70 ADC_LCBR1 Limit Check Boundary Register 1 Reset Value: B0 RMAP: 0, PAGE: 0...
Page 580 XC82x Analog to Digital Converter re-directs the conversion request for CH0 to CHx, but taking into account the settings for CH0. Although the same analog input (CHx) has been measured, the conversion results can be stored and retrieved from result registers RESRx (conversion triggered for CHx) and RESR0 (conversion triggered for CH0).
Page 581 XC82x Analog to Digital Converter The Alias Register specifies replacement channel numbers for CH0, i.e. CH0 will use the respective channel numbers when requested. The programmed alias channel number controls the analog input multiplexer (of the converter). The original channel number controls all other internal actions and the synchronization request.
Page 582 XC82x Analog to Digital Converter 21.8.5 Out of Range Comparator The out of range comparator mechanism is build into every ADC channels and detects voltages higher or lower than Vddp. Before using the out of range comparator, it has to be enabled by setting the bits at ADC_ENORC.ENORCx and configuring it to detect...
Page 583 XC82x Analog to Digital Converter The bit fields in these registers enables the out of range comparator in the ADC channel. ADC_ENORC Enable Out Of Range Comparator Register(D3 Reset Value: 00 RMAP: 0, PAGE: 0 ENORC7 ENORC6 ENORC5 ENORC4 ENORC3...
Page 584 XC82x Analog to Digital Converter The bit fields in this register selects for detection of voltages higher or lower than Vddp at each input ADC channels that triggers the out of range comparator. ADC_CORC Configure Out Of Range Comparator Register(D2...
Page 585 XC82x Analog to Digital Converter The bit fields in these registers indicates if a voltage out of range have occured for the corresponding analog input channels. If a voltage out of range have occured it will be latched to 1 in this register. The event flag can be cleared by writing a 0 to this register.
Page 586: Conversion Timing
XC82x Analog to Digital Converter 21.8.6 Conversion Timing The total time required for a conversion depends on several user-definable factors: • The ADC conversion clock frequency, where / (CTC+3) ADCI = (2 + STC) × • The selected sample time, where...
Page 587 XC82x Analog to Digital Converter Table 21-6 Sample Time Sample Time ADC_INPCR0.STC (bin) 0000 ADCI 0001 ADCI 17 x 1111 ADCI   × × ----------------- - 1.104us (21.3)   48Mhz conv User’s Manual 21-62 V1.0, 2010-02 ADC, V2.1...
Page 588 XC82x Analog to Digital Converter 21.8.7 Channel Events and Interrupts A channel event interrupt can be generated based on a channel event according to the structure shown in Figure 21-20. If a channel event is detected, it sets the corresponding indication flag in register ADC_CHINFR.
Page 589: Conversion Result Handling
XC82x Analog to Digital Converter 21.9 Conversion Result Handling The conversion results of each analog input channel can be stored in one of 4 conversion result registers (selected by bitfield RESRSEL in the associated channel control register CHCTRx). This structure provides different locations for the conversion results of different groups of channels.
Page 590 XC82x Analog to Digital Converter Up to 4 result values can be added in each result register. This reduces the frequency of interrupts generated by the ADC. • Standard application read view (RESRxL/H): – 8bit conversion mode with Data Reduction and Digital Low Pass Filter disabled.
Page 591 XC82x Analog to Digital Converter indicate the channel number whose conversion triggered the result event , bit 7-5 returns bits 2-0 of the accumulated result. In ADC_RESRxH (x=0-3) bits 7-0 returns bit 10-3 of the accumulated result. • Digital low pass filtered application read view (RESRxL/H): 10bit conversion mode with Data Reduction Disabled and Digital Low Pass Filter enabled.
Page 592 XC82x Analog to Digital Converter Result Read View (SFR Page 2) 8-bit conversion (with accum ulation , 1 conversion ) R ESR xH R ESR xL R7 R6 R5 R4 R3 R2 R1 VF DRC CHNR 8-bit conversion (accum ulated 9 -bit, 2...
Page 593 XC82x Analog to Digital Converter The standard read views of the result registers consists of ADC_RESRxL and ADC_RESRxH which delivers the conversion result and the related channel number. The corresponding valid flag is cleared when register RESRx is read (application view).
Page 594 XC82x Analog to Digital Converter Field Bits Type Description Valid Flag for Result Register x This bit indicates that the contents of the result register x are valid. The result register x does not contain valid data. The result register x contains valid data.
Page 595 XC82x Analog to Digital Converter Field Bits Type Description CHNR [2:0] Channel Number This bit field contains the channel number of the latest register update. Note: Bit 2is only applicable for devices that have 8 ADC channels. For channels not implemented, these bits should be treated as Reserved bits of type ‘r’...
Page 596 XC82x Analog to Digital Converter Field Bits Type Description RESULT[9:3] [6:0] Conversion Result This bit field contains the conversion result or the result of the data reduction filter. Reserved Returns 0 if read; should be written with 0. ADC_RESRxL (x = 0 - 2) Result Register x Low, View Acc.
Page 597 XC82x Analog to Digital Converter Field Bits Type Description Valid Flag for Result Register x This bit indicates that the contents of the result register x are valid. The result register x does not contain valid data. The result register x contains valid data.
Page 598 XC82x Analog to Digital Converter Field Bits Type Description CHNR [2:0] Channel Number This bit field contains the channel number of the latest register update. Note: Bit 2is only applicable for devices that have 8 ADC channels. For channels not implemented, these bits should be treated as Reserved bits of type ‘r’...
Page 599 XC82x Analog to Digital Converter Field Bits Type Description RESULT[9:3] [6:0] Conversion Result This bit field contains the conversion result or the result of the data reduction filter. Reserved Returns 0 if read; should be written with 0. ADC_RESRxL (x = 0 - 2) Result Register x Low, View Acc.
Page 600 XC82x Analog to Digital Converter Field Bits Type Description Valid Flag for Result Register x This bit indicates that the contents of the result register x are valid. The result register x does not contain valid data. The result register x contains valid data.
Page 601 XC82x Analog to Digital Converter Field Bits Type Description CHNR [2:0] Channel Number This bit field contains the channel number of the latest register update. Note: Bit 2is only applicable for devices that have 8 ADC channels. For channels not implemented, these bits should be treated as Reserved bits of type ‘r’...
Page 602 XC82x Analog to Digital Converter The Result Control Registers control the behavior of the result registers and monitor their status. ADC_RCRx (x = 0 - 3) Result Control Register x + x * 1) Reset Value: 00 RMAP: 0, PAGE: 4...
Page 603 XC82x Analog to Digital Converter Field Bits Type Description Wait-for-Read Mode This bit enables the wait-for-read mode for result register x. The wait-for-read mode is disabled. The wait-for-read mode is enabled. VFCTR Valid Flag Control This bit enables the reset of valid flag (by read access to high byte) for result register x.
Page 604: Wait-For-Read Mode
XC82x Analog to Digital Converter The Valid Flag Register summarizes the flags indicating that the corresponding result register contents are valid. ADC_VFCR Valid Flag Clear Register Reset Value: 00 RMAP: 0, PAGE: 4 VFC3 VFC2 VFC1 VFC0 Field Bits Type Description...
Page 605 XC82x Analog to Digital Converter If two request sources target the same result register with wait-for-read mode selected, a higher priority source cannot interrupt a lower priority conversion request started before the higher priority source has requested its conversion. Cancel-inject-repeat mode does not work in this case.
Page 606 XC82x Analog to Digital Converter The digital low pass filter pre-processes the result values by averaging the previous and current results to remove any transient noise voltages that is measured. Standard Data Reduction Mode The data reduction mode can be used as digital filter for anti-aliasing or decimation purposes.
Page 607 XC82x Analog to Digital Converter • If DRC becomes 0, either decremented from 1 (t2, t4, t6, t8 in the example) or loaded from DRCTR, the valid bit for the respective result register is set and a result register event occurs.
Page 608 XC82x Analog to Digital Converter 21.11 Interrupt Request Handling Interrupts can be generated by several types of events. Each ADC kernel provides 2 service request output signals (ADCx_SR[1:0]) connected to interrupt nodes. Four types of events can generate interrupt requests: •...
Page 609 XC82x Analog to Digital Converter The Event indication Flag Register ADC_EVINFR monitors both the detected request source events (flags EVINF0-EVINF1) and the result events (flags EVINF4-EVINF7). ADC_EVINFR Event Interrupt Flag Register Reset Value: 00 RMAP: 0, PAGE: 5 EVINF7 EVINF6...
Page 610 XC82x Analog to Digital Converter The Event Interrupt Set Flag Register ADC_EVINSR sets the corresponding bit at ADC_EVINFR and generates an interrupt request when the associated bit is written. ADC_EVINSR Event Interrupt Set Flag Register Reset Value: 00 RMAP: 0, PAGE: 5...
Page 611 XC82x Analog to Digital Converter Writing a 1 to a bit position in the Event Indication Clear Register ADC_EVINCR clears the corresponding event indication flag EVINFx in register ADC_EVINFR. If a request source or result event is detected when the corresponding bit position is written with a 1, flag EVINFx is cleared.
Page 612 XC82x Analog to Digital Converter The Channel Event Indication Flag Register CHINFR monitors the detected channel events for channels 0 … 7 ADC_CHINFR Channel Interrupt Flag Register Reset Value: 00 RMAP: 0, PAGE: 5 CHINF7 CHINF6 CHINF5 CHINF4 CHINF3 CHINF2...
Page 613 XC82x Analog to Digital Converter Writing 1 to a bit of the CHINSR register sets the corresponding bit and generates the associated interrupt request. Writing a 0 has no effect ADC_CHINSR Channel Interrupt Set Register Reset Value: 00 RMAP: 0, PAGE: 5...
Page 614 XC82x Analog to Digital Converter Writing a 1 to a bit position in the channel indication clear register CHINCR clears the corresponding channel event indication flag CHINFx in register ADC_CHINFR. If a channel event is detected when the corresponding bit position is written with a 1, flag CHINFx is cleared.
Page 615 XC82x Analog to Digital Converter Table 21-8 SFR Address Listing for Pages 4 – 7 Address Page 4 Page 5 Page 6 Page 7 RCR0 ADC_CHINFR ADC_CRCR1 RCR1 ADC_CHINCR ADC_CRPR1 RCR2 ADC_CHINSR ADC_CRMR1 RCR3 ADC_QMR0 ADC_VFCR ADC_EVINFR ADC_QSR0 ADC_ALR0 ADC_EVINCR...
Page 616 XC82x Boot ROM User Routines Boot ROM User Routines The Boot ROM User Routines provides a set of useful routines that can be called by user application. These routines have been developed as part of the Boot ROM functionality and are provided to the user via a Boot ROM User Routine table. User application would...
Page 617 XC82x Boot ROM User Routines Table 22-2 Calling Flash User Routines Name Called from Target BR_FLASH_PROGRAM Flash Bank 0 Flash Bank 0 XRAM Flash Bank 0 BR_FLASH_ERASE BR_FLASH_BACKGROUND_PROGRAM XRAM Flash Bank 0 BR_FLASH_BACKGROUND_ERASE BR_FLASH_BACKGROUND_ERASE_ABORT 22.1 Flash Bank Read Mode Status Subroutine...
Page 618 XC82x Boot ROM User Routines 22.2 Get 4 Bytes Information This routine allow the tool chain software or even user code to read out the Chip Identification Number (see Chapter 1.4) or User Identification Number (USER_ID; see Chapter 5.1) for device.
Page 619 XC82x Boot ROM User Routines 22.3 Feature Setting Subroutine Feature Setting subroutine is provided in the Boot ROM to initialize some settings. Currently only 2 options provided, CLKMODE setting (BR_CLKMODE_SETTING) and programming of USER_ID (BR_PROG_USER_ID). See The CLKMODE setting sets the frequency to 8MHz or 24MHz while USER_ID programming programs the 4 bytes user identification (USER_ID) information into device .
Page 620 XC82x Boot ROM User Routines Table 22-6 Specifications of Program USER_ID subroutine Subroutine BR_PROG_USER_ID (BR_FEATURE_SETTING - Option 1) Input R7 of current Register Bank: Option Option 1-BR_PROG_USER_ID Others: Reserved (Invalid options) R5 of current Register Bank: IRAM start address for 4-byte User Identification Number...
Page 621 XC82x Boot ROM User Routines Note: Clock Frequency and BGSEL SFR field bit are not modified in this routine. These field bits can be modified by user first before calling this user-routine for desired baud rate and clock frequency Note: SPD setting is not disabled upon entering this user-routine. User must ensure that there are no conflicts in the port pins used by SPD and auto baud.
Page 622 XC82x Boot ROM User Routines Table 22-8 Specifications of BR_UART_BSL subroutine Subroutine BR_UART_BSL Input IEN0.EA = 0 NMICON = 0x00 BCON.BGSEL SFR field bit to be set accordingly Stack Pointer (SP) Setting: 0x07 <= SP <= 0x60 or SP = 0xE0...
Page 623 XC82x Boot ROM User Routines Table 22-9 Specifications of FLASH_PROGRAM subroutine (cont’d) Input Flash WL aligned address to be programmed R6 of current Register Bank: DPH R7 of current Register Bank: DPL R5 of current Register Bank: IRAM start address for 32-byte Flash data 32-byte Flash data All interrupts including NMI must be disabled (IEN0.EA=0,...
Page 624 XC82x Boot ROM User Routines Table 22-10 Specifications of FLASH_BACKGROUND_PROGRAM subroutine Input Flash WL aligned address to be programmed: R6 of current Register Bank: DPH R7 of current Register Bank: DPL R5 of current Register Bank: IRAM start address for 32-byte Flash data 32-byte Flash data Flash NMI (NMICON.NMIFLASH) is enabled (1) or disabled (0)
Page 625 XC82x Boot ROM User Routines Note: As program will return to user code after erasing is completed, customer should take care that they do not erase their user program code as well. Note: When invalid/No input(s) is provided for this routine, C flag will be set, and routine will be exited.
Page 626 Each complete erase operation on a Flash bank requires approximately 100 ms, during which read and program operations on the Flash bank cannot be performed. For the XC82x, provision has been made to allow an on-going erase operation (type 2, BR_FLASH_BACKGROUND_ERASE) to be interrupted so that higher priority tasks such as reading/programming of critical data from/to the Flash bank can be performed.
Page 627 XC82x Boot ROM User Routines • Maximum allowable number of aborted erase for each D-Flash sector during lifetime is 2500. The Flash erase abort subroutine call cannot be performed anytime within 5 ms after the erase operation has started. This is a strict requirement that must be ensured by the user.
Page 628 EEPROM Emulation ROM Library User application would be able to call these routines by calling the functions provided in Table 23-1 for XC82x device. Details of the ROM library are covered in its respective section. Table 23-1 XC82x ROM Library function and its Address...
Page 629 XC82x ROM Library Table 23-1 XC82x ROM Library function and its Address (cont’d) Addr Name Description 0xDFD5 FIXEEPROM EEPROM Emulation ROM Library 0xDFD8 READEEPROM EEPROM Emulation ROM Library 0xDFDB WRITEEEPROM EEPROM Emulation ROM Library 1) These functions are useful for space vector modulation, as these functions can used as move accelerator i.e.
Page 630 XC82x ROM Library 23.1 Fixed Point ROM Library The Fixed Point Library contains a list of routines that recite in ROM that are accessible to users. The definitions and specifications of the library routines are explained in the following sections.
Page 631 XC82x ROM Library Code Example: //global variables data int Speed; data int Speed_ref; data int Speed_kp; data int P_Speed; //program Speed = 16288 Speed_ref = 4000; Speed_kp = 4096; P_Speed = P_controller_G16(Speed_ref, Speed, (char idata *) &Speed_kp); //P_speed = 0x7F40 23.1.2...
Page 632 XC82x ROM Library Table 23-3 Specifications of PI Controller Routine (cont’d) Input R7, R6 (MSB), Ref_val = 16 bit Reference value R5, R4 (MSB), Acutal_val = 16 bit Actual value R3 = idata pointer to Y(k-1)_H Remark Required structure: Struct{...
Page 633 XC82x ROM Library Speed_control.PI_SAT_HH = 0x1F; PI_Speed = PI_controller_G16(Speed_ref, Speed, &Speed_control); //PI_Speed = 0x108E 23.1.3 PT1_24 Controller Routine The PT1_24 controller routine is a digital lowpass filter defined as: (23.3) – × Y(k) Y(k-1) X(k) Y(k-1) – where • Y(k): PT1_24 controller output •...
Page 634 XC82x ROM Library data int angle_old; //program Speed[0] = 0xF8; Speed[1] = 0xF3; Speed[2] = 0xCB; angle_new = 0x1800; angle_old = 0x0800; result = PT1_24(angle_new - angle_old, 5, &speed); //result = 0xF9AC; 23.1.4 PT1_32 Controller Routine The PT1_32 controller routine is an integrator defined as: (23.4)
Page 635 XC82x ROM Library Table 23-5 Specifications of PT1_32 Controller Routine (cont’d) Resource PSW, A, MDU used/destroyed R0 of current Register Bank Code Example: //global variables data int result; data int Integrator[2]; //program Integrator[0] = 0xFF12; Integrator[1] = 0xE828; MDU_MD4 = 0x1F;//Low byte Z1 MDU_MD5 = 0x00;...
Page 636 XC82x ROM Library Table 23-6 Specifications of Clarke Transform Routine C-Prototype void Clarke(int idata *I_phaseAB, int idata *I_alphabeta) Input R7 = idata pointer to I_phaseA_H R5 = idata pointer to I_alpha_H Remark char idata *I_phaseAB Expected addreass arrangement in IRAM:...
Page 637 XC82x ROM Library 23.2 LED and Touch-Sense Controller ROM Library The LEDTS ROM Library contains two routines that recite in ROM that are accessible to users. The definitions and specifications of the library routines are organized into the following major sections.
Page 638 XC82x ROM Library 23.2.1 SET_LDLINE_CMP Function (LED and TS) This function programs sfrs LTS_LDLINE and LTS_COMPARE (brightness/oscillation window) for LED and/or Touch-sense, based on the users’ input parameters. The function takes sfr bit FNCOL value direct from the sfr LTS_GLOBCTL1 to synchronize...
Page 639 XC82x ROM Library Figure 23-2 SET_LDLINE_CMP Function - SFR Settings User’s Manual 23-12 V1.0, 2010-02 ROM Library, V0.5...
Page 640 XC82x ROM Library 23.2.1.1 Inputs for SET_LDLINE_CMP Function (LED only) If only LED module is enabled, the inputs overview is shown in Table 23-8. Examples of input parameters for 2, 4, 6 or 8 LEDs enabled are also shown in Figure 23-3.
Page 641 XC82x ROM Library Eg. 8 LED + No TS enabled Eg. 2 LED + No TS enabled Eg. 4 LED + No TS enabled Eg. 6 LED + No TS enabled LDLINE(A) LDLINE(A) LDLINE(A) LDLINE(A) LDLINE(0) R7 + 1 LDLINE(0)
Page 642 XC82x ROM Library 23.2.1.2 Inputs for SET_LDLINE_CMP Function (Touch-sense only) If only Touch-sense module is enabled, the inputs overview is shown in Table 23-9, Table 23-10 for common and different compare parameters setting (for oscillation window) respectively. Examples of input parameters are also shown in Figure 23-4.
Page 643 XC82x ROM Library Table 23-10 Specifications of Setting LDLINE & Different COMPARE (TS only) Input R7 of current Register Bank: Start IRAM address of LDLINE parameter R5 of current Register Bank: Start IRAM address of CMP_OPTION & COMPARE parameters LDLINE parameters programmed into IRAM, address R7.
Page 644 XC82x ROM Library 23.2.1.3 Inputs for SET_LDLINE_CMP Function (LED and TS) If both LED and Touch-sense modules are enabled, the inputs overview is shown in Table 23-11 Table 23-12 for common and different compare parameters setting (for oscillation window) respectively. Examples of input parameters are also shown in...
Page 645 XC82x ROM Library 1) Depending how many LED(s) is/are enabled; y = no. of LED(s) enabled. Maximum LEDs enabled are 7 when TS is enabled. 2) This common Compare parameter cannot be 0xFF value. Table 23-12 Specifications of Setting LDLINE & Different COMPARE (LEDTS)
Page 646 XC82x ROM Library Eg. No LED + 8 TS PAD enabled Eg. 2 LED + 2 TS PAD enabled Eg. 2 LED + 2 TS PAD enabled Eg. No LED + 8 TS PAD enabled TS PADTx has different TS PADTx has different compare...
Page 647 XC82x ROM Library Eg. 4 LED + 5 TS PAD enabled Eg. 4 LED + 5 TS PAD enabled Eg. 7 LED + 8 TS PAD enabled Eg. 7 LED + 8 TS PAD enabled TS PADTx has different TS PADTx has common...
Page 648 XC82x ROM Library 23.2.2 FINDTOUCHEDPAD Function (TS) The touch-sense concept is based on a pad being a capacitor between the padline and ground. A finger approaching this pad will alter the capacitance. To measure this change, the arrangement is such that together with a resistor and the I/O pad we have an RC oscillator.
Page 649 XC82x ROM Library Figure 23-7 FINDTOUCHEDPAD Function - SFR Settings User’s Manual 23-22 V1.0, 2010-02 ROM Library, V0.5...
Page 650 XC82x ROM Library This function calculates a running average for each Pad Turn to eliminate any spurious peaks and troughs in the pad frequencies and to create a stable value from which the trip points can be calculated. The average is derived from the total values from number of samples (input, AccumulatorCounter) and included low pass filter gain (input, divisor n).
Page 651 XC82x ROM Library Table 23-13 Specifications of Find Touched Pad Subroutine (cont’d) IRAM address 0x32 Subtraction Option or Subtraction m Address The option to choose between common subtraction value or different respective subtraction values for all touch pads. If option is 0x00, it means common subtraction is chosen for all touch pads.
Page 652 XC82x ROM Library Table 23-13 Specifications of Find Touched Pad Subroutine (cont’d) IRAM address 0x2E PadResult Status Bit 0 indicates the result status of PADT0 Bit 1 indicates the result status of PADT1 Bit 7 indicates the result flag of PADT7 This byte/bit(s) indicate(s) that the pad(s) is/are touched within valid range.
Page 653 XC82x ROM Library cannot enable 3 PADTx and defined them as PADT0, PADT4 and PADT6 for example, it has to be PADT0, PADT1 and PADT2. • PADTx will remains for (AccumulatorCounter+1 ) time, and the function will increment the PADTx when TSCTR_COUNTER is 0x00 and will repeat back to PADT0 once the highest enabled PADTx is set.
Page 654 XC82x ROM Library 23.2.2.1 Outputs of Function This function checks if the current counter value is below the trip point and sets a flag in a variable called PadFlag Status. Once a PadFlag Status has been set, a software implemented Pad Down Counter (PDC) starts to decrement each time the function is called provided the PadFlag is set.
Page 655 XC82x ROM Library Field Bits Type Description Pad Line3 Pad Line 3 of PadFlag , Pad not touched , Pad touched Pad Line4 Pad Line 4 of PadFlag , Pad not touched , Pad touched Pad Line5 Pad Line 5 of PadFlag...
Page 656 XC82x ROM Library Field Bits Type Description Pad Line3 Pad Line 3 of PadResult , Pad not valid , Pad valid Pad Line4 Pad Line 4 of PadResult , Pad not valid , Pad valid Pad Line5 Pad Line 5 of PadResult...
Page 657 XC82x ROM Library Field Bits Type Description Pad Line3 Pad Line 3 of PadError , Pad OK , Pad ERROR Pad Line4 Pad Line 4 of PadError , Pad OK , Pad ERROR Pad Line5 Pad Line 5 of PadError...
Page 658 XC82x ROM Library The LowTrip (Trip point) value is calculated by subtracting user-defined input subtraction m from the Average. (23.9) LOWTRIPL/H(x) AVERAGEL/H(x) SUBTRACTION m – With the LowTrip value calculated from the Average value, the comparison is done with the current accumulated LTS_TSCTR values in TOTAL_TSCTRL/H * 2 where n is the user-defined input Divisor n.
Page 659 XC82x ROM Library total TSCTR >= LowTrip IDLE total TSCTR < LowTrip ERROR PDC = 0 touched error flag cleared byuser total TSCTR >= LowTrip RESULT PDC < SC released result flag PDC > SC cleared by user Figure 23-8 State diagram...
Page 660 XC82x ROM Library On Enter: check if pad result is cleared by the user, if not, exit. On Exit: IDLE Pad Error: On Enter: check if pad error is cleared by the user, if not, exit. On Exit: IDLE Pad Down Counter - PDC When function detects an initial padtouch, it will initialize the PDC value to 0xFF.
Page 661 XC82x ROM Library Average[0] Trip point Tsctrval long shor PadFlag[0] Short PDC PadResult[0] PadError[0] Time slices Cleared by the application Figure 23-10 Timing Diagram Padline 0 used for the example above to show the interaction between PadFlags, PadResult, PadError and PDC. The trip point (LowTrip) can be fixed or as in this...
Page 662 XC82x ROM Library Time Slice, Time Frame and Period Definition There is a Time Slice, Time Frame and Periods naming convention. There is hardware- controlled scheme period and software-controlled ROM Library scheme period (Single Pad Accumulated Count Period and All Enabled Pads Accumulated Count Period). The...
Page 663 XC82x ROM Library For example, 7 LEDs and 3 Touch Sense Pad Turns are enabled 1 Time-Slice PADT0 PADT0 PADT1 PADT2 5 4 3 2 1 0 TS 5 4 3 2 1 0 TS 5 4 3 2 1...
Page 664 XC82x ROM Library 23.2.3 Use of the functions in Interrupts With correct inputs prepared for the functions, the functions can be called from Time Slice interrupt or Time Frame interrupt, depending on whether LED or/and TS is enabled. Figure 23-12...
Page 665 XC82x ROM Library * function in ROM When LED and TS are enabled . When Time Slice and Time Frame interrupts are enabled Time Slice Interrupt (TimeSliceFlag) LED Column Data for ** Called every time slice display, COMPARE regardless of touch sense...
Page 666 XC82x ROM Library 23.3 MDU ROM Library (MATH Function) The MDU ROM Library (MATH Function) contains 4 routines that reside in ROM that are accessible to users. The call functions for MDU ROM Library is listed in Table 23-14 Table 23-14 MDU ROM Library (MATH Function) Routine Table...
Page 667 XC82x ROM Library 23.3.2 Long Multiplication (23.18) × Output is Result of Value1 Value2 Table 23-16 Specifications of 32-bit Multiplication Subroutine Subroutine ?C?LMUL_XC Address DFC3 Input R7 of current Register Bank: Value1 (Bits 7-0) R6 of current Register Bank: Value1 (Bits 15-8)
Page 668 XC82x ROM Library 23.3.3 Integer Division (23.19) Value1 ------------------ - Outputs are Result and Remainder of Value2 Table 23-17 Specifications of 16/16-bit Division Subroutine Subroutine ?C?UIDIV_XC Address DFC6 Input R7 of current Register Bank: Value1 (Low Byte) R6 of current Register Bank:...
Page 669 XC82x ROM Library 23.3.4 Long Division (23.20) Value1 ------------------ - Outputs are Result and Remainder of Value2 Table 23-18 Specifications of 32/32-bit Division Subroutine Subroutine ?C?ULDIV_XC Address DFC9 Input R7 of current Register Bank: Value1 (Bits 7-0) R6 of current Register Bank:...
Page 670 XC82x ROM Library Table 23-18 Specifications of 32/32-bit Division Subroutine (cont’d) Output R7 of current Register Bank: ÷ Result of [Value1 Value2] (Bits 7-0) R6 of current Register Bank: ÷ Result of [Value1 Value2] (Bits 15-8) R5 of current Register Bank: ÷...
Page 671: System Requirement
ROM Library 23.4 EEPROM Emulation ROM Library The XC82x provide EEPROM emulation functionality via the ROM library. The EEPROM is emulated using the on-chip flash memory. The ROM library provide a framework to access the emulated EEPROM. The ROM library used the following application note as a reference, AP0805710 XC866/XC886/XC888 EEPROM EMULATION.
Page 672 XC82x ROM Library The logical address provides a convenient abstraction so that user application don’t need to deal with the actual physical flash address that is used for emulation. The status byte is used by the ROM library to manage the EEPROM emulation. It is written at the end of each flash wordline.
Page 673: Api Description
XC82x ROM Library stored in the IRAM, user application will then need to update the relevant data in IRAM with the desired data. This is then followed by a call to write function to program the data into the emulated EEPROM.
Page 674 XC82x ROM Library InitEEPROM() and WriteEEPROM(). DataSize store the EEPROM emulation dataset size EEPROMInfo should not be modified directly by user. It only should be modified by functions provided by EEPROM emulation API. 23.4.4.3 Functions The EEPROM emulation API provide 4 functions •...
Page 675 XC82x ROM Library The “active sector” is selected based on the sector containing a valid status byte. If both logical sector contains valid status byte, the one containing the least amount of valid status byte is selected as the active sector. Additionally InitEEPROM() will return an error status requesting the sector with the most valid status byte to be erased.
Page 676 XC82x ROM Library WriteEEPROM Table 23-23 WriteEEPROM Function name WriteEEPROM Function prototype void WriteEEPROM(unsigned char address, char idata * src, EEPROMInfo *config) Input address - Logical address of emulated EEPROM to write to src - Pointer to 32 bytes of data in IRAM that is to be written...
Page 677 XC82x ROM Library ReadEEPROM() will search the current "active sector" for the most current data based on the given "address". It will always return 32 bytes of data i.e. 31 data byte + 1 status bytes. The "address" takes the form of a number from 0 to 3. For dataset size of 32bytes, only address 0 is valid.
Page 678 XC82x ROM Library /*Check that EEPROM sectors are in valid condition*/ eeprom_status = InitEEPROM(MODE_3, &config); if (0 != eeprom_status){ /*Fatal failure in EEPROM*/ while(1); /*User application code*/ /*Example of reading and writing to emulated EEPROM*/ /*Get current data*/ ReadEEPROM(WL_1, &buffer, &config);...
Page 679: Keyword Index
XC82x Keyword Index Keyword Index Registers CHINCR 21-89 CHINFR 21-87 Accumulated Application Read View CHINSR 21-88 21-65 CRCR1 21-23 Alias Feature 21-54 CRMR1 21-21 Boundary Flag 21-53 CRPR1 21-24 Channel Scan Request Source Han- ENORC 21-58 dling 21-19 ETRCR 21-37...
Page 680 XC82x Keyword Index User mode (productive) 5-4 T12DTCL 20-49 Boot-loader 4-6, 4-11, 5-4 T12H 20-43 Brownout reset 7-7 T12L 20-43 Buffer mechanism 4-3 T12MSELH 20-55 T12MSELL 20-55 T12PRH 20-44 CCU6 T12PRL 20-44 Block Diagram 20-3 T13H 20-79 Hall Sensor Mode 20-90...
Page 681 XC82x Keyword Index Registers 2-3 Sector 4-3 ACC 2-3 Flash program memory 3-1 B Register 2-3 Data Pointer 2-3 PCON 2-6 Gate disturb 4-6 PSW 2-3 GPIO 11-1 Stack Pointer 2-3 Hamming code 4-9 Data memory 3-2 High-impedance 11-2 Debug System 10-1...
Page 682 XC82x Keyword Index Structure 9-10 Address extension by mapping 3-4 Mapped Type 1 9-11 Type 2 9-11 Standard Interrupt Response Time 9-13 Address extension by paging 3-7 Local address extension LED and Touch-Sense Controller 19-1 LED Controller 19-1 Save and restore...
Page 683 XC82x Keyword Index Port data out register 11-7 Continous transfer operation 18-14 Pull-Up/Pull-Down device register Data width 18-9 11-9 Error detection 18-16 Px_ALTSELn 11-10 Baud rate error 18-17 Px_OD 11-8 Phase error 18-17 Px_PUDEN 11-9 Receive error 18-17 Px_PUDSEL 11-9...
Page 684 XC82x Keyword Index TLx 13-9 TMOD 13-11 TLx 13-9 TMOD 13-11 Touch-Sense Controller 19-1 UART 16-1–16-25 Baud rate 16-9 Baud rate generator 16-9 Interrupt requests 16-6 Mode 0, 8-bit shift register 16-3 Mode 1, 8-bit UART 16-4 Mode 2, 9-bit UART 16-6...
Page 685: Register Index
XC82x Register Index Register Index CCU6_MCMOUTSL 20-106 CCU6_MODCTRH 20-99 BCON 16-22 CCU6_MODCTRL 20-98 BGH 16-25 CCU6_PISEL0H 20-128 BGL 16-24 CCU6_PISEL0L 20-127 CCU6_PISEL2 20-129 CCU6_PSLR 20-103 CCU6_CC60RH 20-46 CCU6_T12DTCH 20-49 CCU6_CC60RL 20-46 CCU6_T12DTCL 20-49 CCU6_CC60SRH 20-47 CCU6_T12H 20-43 CCU6_CC60SRL 20-47 CCU6_T12L 20-43...
Page 686 XC82x Register Index EVINFR 21-84 IRCON3 9-26 EVINPR 21-58 EVINSR 21-85 EXICON0 9-21, 9-22 LCBR 21-54 LINST 16-23 LTS_COMPARE 19-23 FEAH 4-10 LTS_GLOBCTL0 19-21 FEAL 4-10 LTS_GLOBCTL1 19-22 LTS_LDLINE 19-25 LTS_LDTSCTL 19-24 GLOBCTR 21-14 LTS_TSCTL 19-26 GLOBSTR 21-15 LTS_TSVAL 19-27...
Page 687 XC82x Register Index P0_PUDEN 11-19 SDCON 7-4 P0_PUDSEL 11-18 SSC_BRH 18-26 P1_ALTSEL0 11-28 SSC_BRL 18-26 P1_ALTSEL1 11-28 SSC_CONH 18-22, 18-24 P1_DATAIN 11-26 SSC_CONL 18-21, 18-24 P1_DATAOUT 11-26 SSC_RBL 18-27 P1_OD 11-27 SSC_TBL 18-27 P1_PUDEN 11-28 SYSCON0 3-6 P1_PUDSEL 11-27 P2_DATAIN 11-33...
Page 688 . i n f i n e o n . c o m Published by Infineon Technologies AG...

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