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Table 17-5
Baud Rate Selection
f
PCLK
8 MHz
24 MHz
The frequency at which the IIC bus is sampled is calculated by the formulae:
To ensure correct detection of START and STOP conditions on the bus, the IIC must
sample the IIC bus at least ten times faster than the bus clock speed of the fastest master
on the bus. The sampling frequency should therefore be at least 1 MHz in standard
mode or 4 MHz in fast mode to guarantee correct operation with other bus masters.
17.5
Clock Synchronization
If another device on the IIC bus drives the clock line when the IIC is in master mode, the
IIC will synchronize its clock to the IIC bus clock. The high period of the clock will be
determined by the device that generates the shortest high clock period. The low period
of the clock will be determined by the device that generates the longest low clock period.
When the IIC is in master mode and is communicating with a slow slave, the slave may
stretch each bit period by holding the SCL line low until it is ready for the next bit. The
IIC will automatically re-synchronize as described above.
When the IIC is in slave mode, it will hold the SCL line low after each byte has been
transferred until IFLG has been cleared in the CNTR register.
17.6
Bus Arbitration
In master mode, the IIC will check that each transmitted logic 1 appears on the IIC bus
as a logic 1. If another device on the bus over-rules and pulls the SDA line low, arbitration
is lost. If arbitration is lost during the transmission of a data byte or a Not-Acknowledge
bit, the IIC will return to idle state. If arbitration is lost during the transmission of an
address, the IIC will switch to slave mode so that it can recognize its own slave address
or the general call address.
User's Manual
IIC, V1.1
Baud Rate = 100 KBaud
PREDIV
BRP+1
1 (1
)
4 (4
H
1 (1
)
12 (C
H
f
SAMP
Baud Rate = 400 KBaud
PREDIV
)
1 (1
)
H
H
)
1 (1
)
H
H
f
PCLK
---------------------
=
PREDIV
2
17-6
XC82x
Inter-IC Bus
BRP+1
1 (1
)
H
3 (3
)
H
(17.2)
V1.0, 2010-02
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