Infineon Technologies TC1728 User Manual page 1256

Table 19-9 Registers Overview - MSC Kernel Registers
Register Register Long Name
Short Name
ID Module Identification Register
USR Upstream Status Register
DSC Downstream Control Register
DSS Downstream Status Register
DD Downstream Data Register
DC Downstream Command Register
DSDSL Downstream Select Data Source Low
Register
DSDSH Downstream Select Data Source High
Register
ESR Emergency Stop Register
UD0 Upstream Data Register 0
UD1 Upstream Data Register 1
UD2 Upstream Data Register 2
UD3 Upstream Data Register 3
ICR Interrupt Control Register
ISR Interrupt Status Register
ISC Interrupt Set Clear Register
OCR Output Control Register
1) The absolute register address is calculated as follows:
Module Base Address (
User's Manual
MSC, V1.37 2009-05
Table 19-8 ) + Offset Address (shown in this column)
Micro Second Channel (MSC)
Offset
Address
08
10
14
18
1C
20
24
28
2C
30
34
38
3C
40
44
48
4C
19-37
TC1728
Description
1)
see
Page 19-38
H
Page 19-39
H
Page 19-41
H
Page 19-44
H
Page 19-59
H
Page 19-59
H
Page 19-46
H
Page 19-47
H
Page 19-48
H
Page 19-60
H
H
H
H
Page 19-49
H
Page 19-52
H
Page 19-54
H
Page 19-56
H
V1.0, 2011-12