Infineon Technologies TC1728 User Manual page 1148

Note: After a hardware reset operation, the two ASC modules are disabled.
Note: The number of module clock cycles (wait states) which are required for a
"destructive read" access (means: flags/bits are set/reset by one read access) to
ASC module register depends on the selected CLC clock frequency, which is
selected via bit field RMC in the CLC register. Therefore, increasing
ASC0_CLC.RMC may result in a longer FPI Bus read cycle access time.
User's Manual
ASC, V1.3 2007-11
Asynchronous/Synchronous Serial Interface (ASC)
17-36
TC1728
V1.0, 2011-12