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Instruction cache
Same code executes concurrently
CPU0
Control
log
Compare (HW)
Shared Bus
Peripheral
Lockstep Architecture
Break-Before-Make
Figure 15-1 Break-After-Make concept
User's Manual
BMU, V2.6
Data SRAMs
CPU1
Monitor
log
15-5
Bus Monitor Unit (BMU)
Instruction
CPU0
cache
Redundant code
Control
executes
Thread
sequentially
time
Shared Bus
Control
Peripheral
Thread
Logger
(BMU)
Compare (PCP)
Lockstep Emulation – Break-After-Make
TC1728
Data
SRAMs
Monitor
Thread
Monitor
Thread
Logger
(PCP)
V1.0, 2011-12
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