Baud Rate - Infineon Technologies TC1728 User Manual

19.1.3.4 Baud Rate

The baud rate of the upstream channel is derived from the MSC module clock
Figure 19-17 shows the configuration of the upstream channel clock circuitry.
f
MSC
Figure 19-17 Upstream Channel Clock Circuitry
The serial data input SI is evaluated with the baud rate clock
cell, and latched in case of a data bit. The baud rate clock
programmable clock divider. The frequency of
cell and therefore the baud rate for the received data. The content of bit field USR.URR
selects the baud rate according
Baud rate
MSC Upstream Channel
Table 19-6 Upstream Channel Divide Factor DF Selection & Baud Rate
USR.URR
000
B
001
B
010
B
011
B
100
B
101
B
110
B
111
B
Note: With the USR.URR = 000
is not possible.
User's Manual
MSC, V1.37 2009-05
USR
URR
Programmable
f
BR
Clock
Divider
Table 19-6. The resulting baud rate formula is:
f
MSC
= ---------- -
DF
Divide Factor DF
reception disabled
4
8
16
32
64
128
256
the upstream channel is disabled and data reception
B
19-25
Micro Second Channel (MSC)
Receive Buffer
f
in the middle of each bit
BR
f
is derived from
BR
f
determines the width of a received bit
BR
Baud Rate
–
f
/4
MSC
f
/8
MSC
f /16
MSC
f
/32
MSC
f
/64
MSC
f /128
MSC
f
/256
MSC
TC1728
f
MSC
SI
MCA06243
f
by a
MSC
(19.2)
V1.0, 2011-12
.