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TC1728
Program Memory Unit (PMU)
5.3
Emulation Memory Interface
In the Emulation Device, an Emulation Memory (EMEM) is provided, which can be used
for calibration via program memory or OLDA overlay. Its base address is A/8FF0 0000
.
H
As for Flash and OVRAM accesses, cached (segment 8
) and non-cached (segment A
)
H
H
accesses can be used for EMEM accesses via PMU.
The Emulation Memory interface shown in
Figure 5-1
is a 64-bit wide memory interface
that controls the CPU-accesses to the Emulation Memory in the Emulation Device. All
widths of write accesses are supported (byte, half-word, word, double-word). CPU-
controlled Load-Modify-Store accesses (with LDMST instruction) are not supported.
In the TC1728 production device, the EMEM interface is always disabled. A CPU read
access from the Emulation Memory region causes a DSE trap and an LMB bus error. If
the Emulation Memory region read access is initiated by a SPB master (e.g. PCP),
additionally a SPB error interrupt is generated. Per default, write accesses to the
Emulation Memory by any master cause an LMB bus error trap in production device.
In the Emulation Device, a LMB bus error trap is reported by the PMU, if the CPU access
can't be handled by the EMEM, for example, when the CPU accesses a trace memory
tile in EMEM. In this case, the EMEM access is aborted by the PMU.
Similar to the internal 8 KB OVRAM, the EMEM can also be used for overlay blocks
dedicated to blocks in the internal Program Flash or to the virtual OLDA memory,
redirecting (in DMI) Flash/OLDA addresses to the Emulation Memory. Also the external
memory is supported for redirection of blocks into the EMEM.
User's Manual
5-7
V1.0, 2011-12
PMU, V1.47
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