Infineon Technologies TC1728 User Manual page 1275

The Output Control Register OCR determines the MSC input/output signal polarities, the
chip select output signal assignment, and the serial output clock generation.
OCR
Output Control Register
31 30 29 28
15 14 13 12
0 CSC
r rw
Field Bits
CLP 0
SLP 1
CSLP 2
ILP 3
User's Manual
MSC, V1.37 2009-05
27 26 25
0
r
11 10 9
CSH CSL
rw rw
Type Description
rw FCLP Line Polarity
0
B
1
B
rw SOP Line Polarity
0
B
1
B
rw Chip Selection Lines Polarity
0
B
1
B
Bit CSLP is buffered during a frame transmission.
This means that any change of CSLP becomes valid
first with the start of the next frame transmission.
rw SDI Line Polarity
0
B
1
B
Micro Second Channel (MSC)
(4C )
H
24 23 22 21
8 7 6 5
CLK
CTR 0
L
rw r
FCLP and FCL signal polarity is identical.
FCLN signal has inverted FCL signal polarity.
FCLP signal has inverted FCL signal polarity.
FCLN and FCL signal polarities are identical.
SOP and SO signal polarity is identical.
SON signal has inverted SO signal polarity.
SOP signal has inverted SO signal polarity.
SON and SO signal polarities are identical.
EN[3:0] and ENL, ENH, ENC signal polarities
are identical (high active).
EN[3:0] signal polarities are inverted (low
active) to the ENL, ENH, ENC signal polarities.
SDI and SI signal polarities are identical.
SDI and SI signal polarities are inverted.
19-56
TC1728
Reset Value: 0000 0000
20 19 18 17
SDISEL
rw
4 3 2 1
CS
ILP SLP CLP
LP
rw rw rw
V1.0, 2011-12
H
16
0
rw