Infineon Technologies TC1728 User Manual page 1024

TC1728
System Timer (STM)
between the two read operations). To enable a synchronous and consistent reading of
the STM content, a capture register (STM_CAP) is implemented. It latches the content
of the high part of the STM each time when one of the registers STM_TIM0 to STM_TIM5
is read. Thus, STM_CAP holds the upper value of the timer at exactly the same time
when the lower part is read. The second read operation would then read the content of
the STM_CAP to get the complete timer value.
The STM can also be read in sections from seven registers, STM_TIM0 through
STM_TIM6, that select increasingly higher-order 32-bit ranges of the STM. These can
be viewed as individual 32-bit timers, each with a different resolution and timing range.
The content of the 56-bit System Timer can be compared against the content of two
compare values stored in the STM_CMP0 and STM_CMP1 registers. Service requests
can be generated on a compare match of the STM with the STM_CMP0 or STM_CMP1
registers.
Figure 14-1 provides an overview on the STM module. It shows the options for reading
parts of the STM content.
User's Manual 14-2 V1.0, 2011-12
STM, V1.6