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TC1728
Interrupt System
31
12
5
0
BIV
0 0 0 0
0
0
0
0
0
PIPN
OR
Resulting Interrupt Vector Table Entry Address
MCA06182
Figure 13-2 Interrupt Vector Table Entry Address Calculation
Left-shifting the PIPN by 5 bits creates entries into the Interrupt Vector Table which are
evenly spaced 8 words apart. If an ISR is very short, it may fit entirely within the eight
words available in the vector table entry. Otherwise, the code at the entry point must
ultimately cause a jump to the rest of the ISR residing elsewhere in memory. Due to the
way the vector table is organized according to the interrupt priorities, the TC1728 offers
an additional option by allowing spanning several Interrupt Vector Table entries as long
as those entries are otherwise unused.
Figure 13-3
illustrates this.
The required size of the Interrupt Vector Table depends only on the range of priority
numbers actually used in a system. Of the 256 vector entries, 255 may be used. Vector
entry 0 is never used, because if ICR.PIPN is 0, the CPU is not interrupted. Distinct
interrupt handlers are supported, but systems requiring fewer entries need not dedicate
the full memory area required by the largest configurations.
User's Manual
13-16
V1.0, 2011-12
Interrupt, V1.4
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