Full-Duplex Operation - Infineon Technologies TC1728 User Manual

Regardless of the selected data width and whether the MSB or the LSB is transmitted
first, the transfer data is always right-aligned in registers TB and RB, with the LSB of the
transfer data in bit 0 of these registers. The data bits are rearranged for transfer by the
internal shift register logic. The unselected bits of TB are ignored, and the unselected bits
of RB will not be valid and should be ignored by the receiver service routine.
The Clock Control allows the adaptation of transmit and receive behavior of the SSC to
a variety of serial interfaces. A specific clock edge (rising or falling) is used to shift out
transmit data, while the other clock edge is used to latch in receive data. Bit CON.PH
selects the leading edge or the trailing edge for each function. Bit CON.PO selects the
level of the clock line in the idle state. For an idle-high clock, the leading edge is a falling
one, a 1-to-0 transition (see
Shift Clock SCLK if:
CON.PO = 0
CON.PH = 0
CON.PO = 0
1)
CON.PH = 1
CON.PO = 1
CON.PH = 0
CON.PO = 1
1)
CON.PH = 1
SSC Pins
MTSR / MRST
1.)
First Bit on MRST is replaced by PISEL.STIP in Slave Mode if CON.PH=1
Figure 18-3 Serial Clock SCLK Phase and Polarity Options

18.1.2.2 Full-Duplex Operation

The description in this section assumes that the SSC is used with software controlled bi-
directional GPIO port lines that have open-drain capability (see also
The various devices are connected through three lines. The definition of these lines is
always determined by the master. The line connected to the master's data output pin
MTSR is the transmit line, the receive line is connected to its data input line MRST, and
the clock line is connected to pin SCLK. Only the device selected for master operation
generates and outputs the serial clock on pin SCLK. All slaves receive this clock, so their
User's Manual
SSC, V1.41 2010-06
Figure 18-3).
Transmit Data
First
1)
Bit
Latch Data
Shift Data
18-6
Synchronous Serial Interface (SSC)
TC1728
Last
Bit
MCT06215_mod
Section 18.1.2.6).
V1.0, 2011-12