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The bits in the STM Interrupt Set/Reset Register make it possible to set or cleared the
compare match interrupt request status flags of register ICR.
STM_ISRR
STM Interrupt Set/Reset Register
31
30
29
28
15
14
13
12
Field
Bits
CMP0IRR
0
CMP0IRS
1
CMP1IRR
2
CMP1IRS
3
0
[31:4] r
Note: Reading register CMISRR always returns 0000 0000
User's Manual
STM, V1.6
(40
27
26
25
24
11
10
9
8
0
r
Type Description
w
Reset Compare Register CMP0 Interrupt Flag
0
Bit ICR.CMP0IR is not changed.
B
1
Bit ICR.CMP0IR is cleared.
B
w
Set Compare Register CMP0 Interrupt Flag
0
Bit ICR.CMP0IR is not changed.
B
1
Bit ICR.CMP0IR is set. The state of bit CMP0IRR
B
is "don't care" in this case.
w
Reset Compare Register CMP1 Interrupt Flag
0
Bit ICR.CMP1IR is not changed.
B
1
Bit ICR.CMP1IR is cleared.
B
w
Set Compare Register CMP1 Interrupt Flag
0
Bit ICR.CMP1IR is not changed.
B
1
Bit ICR.CMP1IR is set. The state of bit CMP1IRR
B
is "don't care" in this case.
Reserved
Read as 0; should be written with 0.
14-19
)
Reset Value: 0000 0000
H
23
22
21
0
r
7
6
5
.
H
TC1728
System Timer (STM)
20
19
18
17
4
3
2
1
CMP
CMP
CMP
1
1
0
IRS
IRR
IRS
w
w
w
V1.0, 2011-12
H
16
0
CMP
0
IRR
w
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