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The parity checking logic in the upstream channel also controls whether start bit and the
two stop bits of the upstream data frame are at correct logic level. If the start bit is not at
low level and the two stop bits are not at high level at the end of the frame reception, the
parity error flag UDx.PERR is set, too.
19.1.3.3 Data Reception
The reception of the upstream frame is started with a falling edge (1-to-0 transition) on
the SI line. When the start bit is detected, serial reception is enabled and the receive
circuit begins to sample the incoming serial data and to buffer it in the receive buffer.
After the second stop bit has been detected, the content of the receive buffer is
transferred to one of four upstream data registers UDx. The receive circuit then waits for
the next start bit (1-to-0 transition) at the SI line. When the content of the receive buffer
has been transferred to UDx, the valid bit UDx.V is set by hardware, and a receive
interrupt can be generated.
Note: The SI input line is the filtered non-inverted (OCR.ILP = 0) or inverted
(OCR.ILP = 1) SDI input signal. The SI input signal selection is described on
Page
19-30).
Frame Reception with Address Field
Frame reception for a 16-bit data frame (see
When the content of the receive buffer has been received completely, it is transferred to
one of the four UDx registers. The two most significant address bits A[3:2] of the received
4-bit address field select the number x of register UDx in which the received frame
content is stored. Register UDx is loaded with the two least significant address bits A0
and A1 (UDx.LABF), the 8-bit data (UDx.DATA), the received parity bit (UDx.P), the
calculated parity bit (UDx.IPF), and the parity checking result (UDx.PERR). Finally, the
valid bit UDx.V is set to indicate that the UDx register contains valid data.
The current state of the frame reception is indicated by the content of an upstream
counter that is readable via bit field USR.UC. The upstream counter is a 5-bit counter
that counts the upstream frame bits during reception. As shown in
upstream counter is loaded with 10000
is again at 00000
B
is finished.
The state of the serial input data line SI is sampled in the middle of a bit cell and shifted
into the receive buffer at the end of the bit cell. The frequency of the shift clock
depends the selected baud rate (see
User's Manual
MSC, V1.37 2009-05
when the second stop bit has been detected and the frame reception
Micro Second Channel (MSC)
Figure
19-16) is selected by USR.UFT = 1.
at the detection of a start bit. It counts down and
B
Page
19-25).
19-23
TC1728
Figure
19-16, the
f
SHIFT
V1.0, 2011-12
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