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Clock control, address decoding, and interrupt service request control are managed
outside the MSC module kernel. Service request outputs are able to trigger an interrupt
or a DMA request.
Features
•
Fast synchronous serial interface to connect power switches in particular, or other
peripheral devices via serial buses
•
High-speed synchronous serial transmission on downstream channel
– Serial output clock frequency:
– Fractional clock divider for precise frequency control of serial clock
– Command, data, and passive frame types
– Start of serial frame: Software-controlled, timer-controlled, or free-running
– Transmission with or without SEL bit
– Flexible chip select generation indicates status during serial frame transmission
– Emergency stop without CPU intervention
•
Low-speed asynchronous serial reception on upstream channel
f
– Baud rate:
MSC
– Standard asynchronous serial frames
– Programmable upstream data frame length (16 or 12 bits)
– Parity error checker
– 8-to-1 input multiplexer for SDI lines
– Built-in spike filter on SDI lines
User's Manual
MSC, V1.37 2009-05
f
FCL
divided by 4, 8, 16, 32, 64, 128, or 256 (
Micro Second Channel (MSC)
=
f
/2 (
f
= 110 MHz)
MSC
MSCmax
19-4
TC1728
f
MSC
f
= 110 MHz)
MSCmax
V1.0, 2011-12
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