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Command Frames
A command frame has two active phase parts, SRL active phase and SRH active phase.
The command frame always starts with a high-level selection bit, independently whether
the selection bit insertion (as defined by bit DSC.ENSELL) is enabled or not. The number
of the bits transmitted during SRL and SRH active phases (except the selection bit) is
defined by bit field DSC.NBC. SRL and SRH are combined to a 32-bit value whose
length can be selected from 0 up to 32 bits. In other words, whenever bits of SRH are
transmitted, they are always preceded by the transmission of the complete SRL content.
During the active phase of a command frame, the enable output signal ENC becomes
active. The enable output signals ENL and ENH remain inactive.
The passive phase of a command frame always has a fixed length of 2 ×
diagram shown in
Figure 19-5
active phase of the command frame (OCR.CLKCTRL = 0).
ENC
Selection Bit
FCL
SO
1
1) Interrupt generation possible
Figure 19-5 Command Frame Layout
User's Manual
MSC, V1.37 2009-05
assumes that the FCL clock is only generated during the
SRL.0
SRL.1
Length defined by DSC.NBC
SRL Active Phase
Active Phase
Micro Second Channel (MSC)
Command Frame
t
FCL
SRL.15
SRH.0
SRH.1
SRH Active Phase
19-7
TC1728
t
FCL
t
2
FCL
SRH.15
Passive Phase
MCT06231
V1.0, 2011-12
. The
1)
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