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The Error Detection and Correction Register ECDR is a test register which is only
writable when the direct RAM access test mode is enabled for the CAN module
(SCU_MEMTEST.MCANDRA = 1).
EDCR
Error Detection and Correction Test Register(080
31
30
29
28
0
r
15
14
13
12
Field
ECCW
EDCDIS
ECCR
SBERR
DBERR
0
User's Manual
MultiCAN, V2.24
27
26
25
DB
ERR
rh
11
10
9
0
r
Bits
Type Description
[6:0]
rw
ECC Write Data
This data is used as ECC for bus write access to
RAM when the error detection and correction is
disabled (EDCDIS = 1).
8
rw
Error Detection and Correction Disable
0
B
1
B
[22:16] rh
ECC Read Data of last RAM Bus Read Access
24
rh
Single Bit Error Flag
This bit indicates whether a single bit error has
occurred with the last RAM read access.
25
rh
Double Bit Error Flag
This bit indicates whether a double bit error has
occurred with the last RAM read access.
7, 23,
r
Reserved
[15:9],
read as 0, should be written with 0.
[31:26]
Controller Area Network Controller (MultiCAN)
)
H
24
23
22
SB
0
ERR
rh
r
8
7
6
EDC
0
DIS
rw
r
Error detection and correction enabled.
Error detection and correction disabled.
20-61
Reset Value: 0000 0000
21
20
19
18
ECCR
rh
5
4
3
2
ECCW
rw
TC1728
H
17
16
1
0
V1.0, 2011-12
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