Bmu: Sist Mode Access Control Register - Infineon Technologies TC1728 User Manual

15.6.5

BMU: SIST Mode Access Control Register

Note: Please see "Error Correction Code (ECC)" on Page 15-18
regarding the use of this register.
This register is ENDINIT protected.
SMACON
SIST Mode Access Control Register
31 30 29 28
15 14 13 12
Field Bits
BMURAM [1:0]
0 [31:2]
User's Manual
BMU, V2.6
(50
27 26 25 24
11 10 9 8
0
r
Type Description
rw SIST mode access control
00 Normal Operation, No Mapping
B
01 Data Array Mapping, no error
B
detection/correction
10 Check Array Mapping, no error
B
detection/correction
11 Data Array Mapping, error detection/correction
B
enabled
r reserved
returns '0' if read; should be written with '0'.
15-45
) Reset Value: 0000 0000
H
23 22 21
0
r
7 6 5
TC1728
Bus Monitor Unit (BMU)
for more information
20 19 18 17
4 3 2 1
BMURAM
V1.0, 2011-12
H
16
0
rw