Infineon Technologies TC1728 User Manual page 1201

f
SSC0
Clock
f
Control
CLC0
Address
Decoder
EIR
TIR
Interrupt
Control
RIR
SSC0_RDR
To
SSC0_TDR
DMA
1)
M/S Select
1)
Enable
1) These lines are
not connected
2) These lines are
connected to V
SS
f
SSC1
Clock
f
Control
CLC1
Address
Decoder
EIR
TIR
Interrupt
Control
RIR
SSC1_RDR
To
SSC1_TDR
DMA
1)
M/S Select
1)
Enable
Figure 18-16 SSC0/SSC1 Module Implementation and Interconnections
User's Manual
SSC, V1.41 2010-06
MRSTA
MRSTB
Master
MTSR
MTSRA
MTSRB
Slave
MRST
SCLKA
Slave
SCLKB
SCLK
Master
SSC0
Module SLSI1
(Kernel)
Slave
SLSI[7:2]
SLSO[2:0]
SLSO[5:3]
SLSO6
Master
SLSO7
SLSOANDI[7:0]
SLSOANDO[7:2]
SLSOANDI[1:0]
SLSOANDI[7:2]
SLSO[2:0]
SLSO3
SLSO6
Master
SLSO[5:4]
SLSO7
SLSOANDO[1:0]
SLSOANDO[7:0]
SLSI1
Slave
SLSI[7:2]
SSC1
MRSTA
Module
MRSTB
Master
(Kernel)
MTSR
MTSRA
MTSRB
Slave
MRST
SCLKA
Slave
SCLKB
SCLK
Master
18-44
Synchronous Serial Interface (SSC)
Port 3
Control
3)
2)
1)
Port 5
Control
2)
1)
Port 2
3)
Control
Port 1
Control
TC1728
P3.4 / MTSR0
A2
P3.3 / MRST0
A1+
P3.2 / SCLK0
A1+
P3.7 / SLSI0
A2
P3.5 / SLSO00 /
SLSO10 /
A1+
SLSOANDO0
P3.6 / SLSO01 /
SLSO11 /
A1+
SLSOANDO1
P3.7 / SLSO02 /
A2
SLSO12
P3.8 / SLSO06
A2
P5.12 / SLSO07
A1+
P2.1 / SLSO03 /
A2
SLSO13
P2.8 / SLSO04 /
A2
SLSO14
P2.9 / SLSO05 /
A2
SLSO15
P2.13 / SLSI1
A1
A1+ P2.12 / MTSR1A
P2.13 / SLSO16
A1+
P2.10 / MRST1A
A1+
P2.11 / SCLK1A
A1+
P1.10 / SLSO17
A1+
P1.8 / MTSR1B
A1+
P1.9 / MRST1B
A1+
P1.11 / SCLK1B
A1+
MCB06225_28
V1.0, 2011-12