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Infineon Technologies TC1784 User Manual

Infineon Technologies TC1784 User Manual

32-bit single-chip microcontroller

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TC1784

32-Bit Single-Chip Microcontroller

User´s Manual

V1.1 2011-05

M i c r o c o n t r o l l e r s

Table of Contents

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Page 1 TC1784 32-Bit Single-Chip Microcontroller User´s Manual V1.1 2011-05 M i c r o c o n t r o l l e r s...
Page 2 Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life.
Page 3 TC1784 32-Bit Single-Chip Microcontroller User´s Manual V1.1 2011-05 M i c r o c o n t r o l l e r s...
Page 4 TC1784 User´s Manual Revision History: V1.1, 2011-05 Previous Version: TS V1.0 Chapter Subjects (major changes since last revision) Changes from TC1784 TS V1.0 to TC1784 UM V1.1 Introduction: • No functional changes CPU: • No functional changes SCU: • Enhanced CHIPID register content •...
Page 5 TC1784 User´s Manual Revision History: V1.1, 2011-05 Interrupt System: • No functional changes System Timer (STM): • Corrected the number of E-RAY interrupts to 10. OCDS: • No functional changes • Replaced OCDS chapter with new User´s Manual chapter ASC: •...
Page 6 We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: mcdocu.comments@infineon.com...
Page 7: Table Of Contents
TC1784 Block Diagram ........1-8...
Page 8 CPU Subsystem ......... . . 2-1 TC1784 Processor Subsystem ....... . 2-1 Central Processing Unit Features .
Page 9 TC1784 Table of Contents 2.12 Implementation Specific Reset Values ......2-58 2.13 CPU Instruction Timing ........2-59 2.13.1...
Page 10 TC1784 Table of Contents Reset Operation ......... . . 3-62 3.2.1...
Page 11 TC1784 Table of Contents 3.5.3 Start-up Registers ........3-117 3.5.3.1...
Page 12 TC1784 Table of Contents 4.2.2.3 Atomic Transfers ........4-4 4.2.3...
Page 13 TC1784 Table of Contents 5.1.2 Firmware Program Structure ....... 5-3 Overlay RAM and Data Acquisition .
Page 14 TC1784 Table of Contents 5.6.7.3 Flash Sleep Mode ........5-89 5.6.7.4...
Page 15 TC1784 Table of Contents 9.1.1 Description Scheme for the Port IO Functions ....9-2 9.1.2 Description of the port operation ......9-3 Port Register Description .
Page 16 TC1784 Table of Contents 9.7.3 Port 4 Registers ......... 9-53 9.7.3.1...
Page 17 TC1784 Table of Contents 10.2.1 High Integrity Operation ........10-2 10.3...
Page 18 TC1784 Table of Contents 10.7.1 Protection of PRAM against FPI Writes ..... . 10-41 10.7.2 Protection of PRAM against Internally Generated PRAM Writes . . 10-41 10.7.2.1...
Page 19 TC1784 Table of Contents 10.17.7 PCP Interrupt Configuration Register, PCP_ICON ... . . 10-75 10.17.8 PCP Stall Status Register, PCP_SSR ..... . . 10-77 10.17.9...
Page 20 Implementing Multiply Algorithms ......10-150 10.22 Implementation of the PCP in the TC1784 ....10-152 10.22.1 PCP Memories .
Page 21 TC1784 Table of Contents 11.2.4 DMA Channel Functionality ....... . 11-7 11.2.4.1...
Page 22 TC1784 Table of Contents 11.4.4 Address Map ......... 11-125 11.5...
Page 23 TC1784 Table of Contents 12.9.4 Command Phase (CP) ........12-26 12.9.5...
Page 24 Interrupt Vector Table ........13-15 13.8 Usage of the TC1784 Interrupt System ......13-18 13.8.1 Spanning Interrupt Service Routines Across Vector Entries .
Page 25 TC1784 Table of Contents 15.3.4 Multi Core Break Switch ....... . . 15-11 15.4...
Page 26 TC1784 Table of Contents 17.1.2.3 Half-Duplex Operation ........17-9 17.1.2.4...
Page 27 TC1784 Table of Contents 18.1.5.1 Data Frame Interrupt ....... . . 18-32 18.1.5.2...
Page 28 TC1784 Table of Contents 19.3.5.4 CAN Frame Counter ........19-24 19.3.5.5...
Page 29 TC1784 Table of Contents 19.5.5.1 CAN Service Request Control Register ....19-118 19.5.6 MultiCAN Module Register Address Map ....19-119 FlexRay™...
Page 30 TC1784 Table of Contents 20.6.5.3 MONITOR_MODE ........20-204 20.6.5.4...
Page 31 TC1784 Table of Contents 20.8.1 Message Buffers with the same Frame ID ....20-258 20.8.2 Data Transfers between IBF / OBF and Message RAM ..20-258 20.9...
Page 32 TC1784 Table of Contents 21.3.6.1 FPC Algorithm ........21-126 21.3.6.2...
Page 33 TC1784 Table of Contents 21.7.4 On-Chip Connections ........21-277 21.7.4.1...
Page 34 Receiver Interrupt Registers ......22-123 22.5 Implementation of the MLI0 in TC1784 ..... . . 22-130 User´s Manual L-28 V1.1, 2011-05...
Page 35 TC1784 Table of Contents 22.5.1 Interfaces of the MLI Modules ......22-130 22.5.2 MLI Module External Registers .
Page 36 TC1784 Table of Contents 23.2.4 Clocking Scheme ........23-24 23.2.5...
Page 37 Implementation ......... 23-132 23.3.1 Request Sources in TC1784 ......23-132 23.3.2 Address Map .
Page 38 TC1784 Table of Contents 24.1 FADC Short Description ........24-2 24.2...
Page 39 TC1784 Table of Contents 24.4 Implementation of FADC ........24-64 24.4.1...
Page 40: Introduction
This TC1784 User´s Manual describes the features of the TC1784 with respect to the TriCore Architecture. Where the TC1784 directly implements TriCore architectural functions, this manual simply refers to those functions as features of the TC1784. In all cases where this manual describes a TC1784 feature without referring to the TriCore Architecture, this means that the TC1784 is a direct implementation of the TriCore Architecture.
Page 41 TC1784 Introduction register names contain a module name prefix, separated by an underscore character “_” from the actual register name (for example, “ASC0_CON”, where “ASC0” is the module name prefix, and “CON” is the kernel register name). In chapters describing the kernels of the peripheral modules, the registers are mainly referenced with their kernel register names.
Page 42: Reserved, Undefined, And Unimplemented Terminology
TC1784 Introduction 1.1.3 Reserved, Undefined, and Unimplemented Terminology In tables where register bit fields are defined, the following conventions are used to indicate undefined and unimplemented function. Furthermore, types of bits and bit fields are defined using the abbreviations as shown in Table 1-1.
Page 43: Abbreviations And Acronyms
TC1784 Introduction Table 1-2 Access Terms Symbol Description Access Mode: Access permitted in User Mode 0 or 1. Reset Value: Value or bit is not changed by a reset operation. Access permitted in Supervisor Mode. Read-only register. Only 32-bit word accesses are permitted to this register/address range.
Page 44 TC1784 Introduction Cyclic Redundancy Code Context Save Area CSFR Core Special Function Register Device Access Port Device Access Server DCACHE Data Cache DFLASH Data Flash Memory DGPR Data General Purpose Register Direct Memory Access Data Memory Interface External Bus Interface...
Page 45 TC1784 Introduction Micro Second Channel Not Connected Non-Maskable Interrupt OCDS On-Chip Debug Support OVRAM Overlay Memory Peripheral Control Processor Program Memory Unit Phase Locked Loop PCODE PCP Code Memory PFLASH Program Flash Memory Program Memory Interface Program Memory Unit PRAM...
Page 46: System Architecture Of The Tc1784
Analog-to-Digital converters. Within the TC1784, all these peripheral units are connected to the TriCore CPU/system via the Flexible Peripheral Interconnect (FPI) Bus and the Local Memory Bus (LMB). Several I/O lines on the TC1784 ports are reserved for these peripheral units to communicate with the external world.
Page 47: Tc1784 Block Diagram
Figure 1-1 shows the block diagram of the TC1784. Pls. note that not all features that are shown in the block diagram are available in the other TC1784 package variants. The TC1782 in the PG-LQFP-176-6 provides no EBU functionality and a reduced maximum frequency.
Page 48: System Features
1) For CPU frequencies > 90 MHz, 2:1 mode has to be enabled. CPU 2:1 mode means: f = 0.5 * f 2) Pls. Note: valid for PG-LFBGA-292-2. Max. frequency for the other TC1784 package variants might be lower. 3) For PCP frequencies > 90 MHz, 2:1 mode has to be enabled. PCP 2:1 mode means: f = 0.5 * f...
Page 49: Cpu Cores Of The Tc1784
TC1784 Introduction 1.2.3 CPU Cores of the TC1784 The TC1784 includes a high Performance CPU and a Peripheral Control Processor. 1.2.3.1 High-performance 32-bit CPU This chapter gives an overview about the TriCore 1 architecture. TriCore (TC1.3.1) Architectural Highlights • Unified RISC MCU/DSP •...
Page 50: High-Performance 32-Bit Peripheral Control Processor
TC1784 Introduction – 0 Kbyte Data Cache (DACHE) • On-chip SRAMs with parity error detection 1.2.3.2 High-performance 32-bit Peripheral Control Processor The PCP is a flexible Peripheral Control Processor optimized for interrupt handling and thus unloading the CPU. Features •...
Page 51: On-Chip System Units
Flexible interrupt-prioritizing scheme with 255 interrupt priority levels per interrupt system 1.3.2 Direct Memory Access Controller The TC1784 includes a fast and flexible DMA controller with 16 independant DMA channels (two DMA Move Engines). Features • 16 independent DMA channels –...
Page 52: System Timer
Dependant on the target/destination address, Read/write requests from the Move Engines are directed to the SPB, LMB, MLIs or to the the Cerberus. 1.3.3 System Timer The TC1784’s STM is designed for global system timing applications requiring both high precision and long range. Features •...
Page 53 TC1784 Introduction Due to the 56-bit width of the STM, it is not possible to read its entire content with one instruction. It needs to be read with two load instructions. Since the timer would continue to count between the two load operations, there is a chance that the two values read are not consistent (due to possible overflow from the low part of the timer to the high part between the two read operations).
Page 54 TC1784 Introduction STM Module STM_CMP0 Compare Register 0 to DMA etc. STM_CMP1 Compare Register 1 Interrupt 56-bit System Timer Control Enable / STM_CAP Disable Clock Control STM_TIM6 STM_TIM5 Address STM_TIM4 Decoder STM_TIM3 PORST STM_TIM2 STM_TIM1 STM_TIM0 MCB06185_mod Figure 1-2 General Block Diagram of the STM Module Registers User´s Manual...
Page 55: System Control Unit
Double Reset Detection: If a Watchdog induced reset occurs twice, a severe system malfunction is assumed and the TC1784 is held in reset until a system / class 0 reset occurs. This prevents the device from being periodically reset if, for instance,...
Page 56: External Interface
The result of the measurement can be read via an DTS register. 1.3.5 General Purpose I/O Ports and Peripheral I/O Lines The TC1784 includes a flexible Ports structure with the following features: Features • Digital General-Purpose Input/Output (GPIO) port lines •...
Page 57: Program Memory Unit (Pmu)
The devices of this family contain at least one Program Memory Unit. This is named “PMU0”. Some devices contain additional PMUs which are named “PMU1”, … In the TC1784, the PMU0 contains the following submodules: • The Flash command and fetch control interface for Program Flash and Data Flash.
Page 58: Boot Rom
OLDA range can also be redirected to an overlay memory. 1.3.6.3 Emulation Memory Interface In TC1784 Emulation Device, an Emulation Memory (EMEM) is provided, which can fully be used for calibration via program memory or OLDA overlay. The Emulation Memory interface shown in...
Page 59 TC1784 Introduction one independent Flash bank, whereas the Data Flash is built of two Flash banks, allowing the following combinations of concurrent Flash operations: • Read code or data from Program Flash, while one bank of Data Flash is busy with a program or erase operation.
Page 60 TC1784 Introduction normally written to Flash by the CPU, but may also be issued by the DMA controller (or OCDS). The Flash also features an advanced read/write protection architecture, including a read protection for the whole Flash array (optionally without Data Flash) and separate write protection for all sectors (only Program Flash).
Page 61 TC1784 Introduction • For further operating conditions see data sheet section “Flash Memory Parameters”. Data Flash Features and Functions • 64 Kbyte on-chip Flash, configured in two independent Flash banks of equal size. • 64 bit read interface. • Erase/program one bank while data read access from the other bank.
Page 62: Data Access Overlay
Overview about the TC1784 development environment: Complete Development Support A variety of software and hardware development tools for the 32-bit microcontroller TC1784 are available from experienced international tool suppliers. The development environment for the Infineon 32-bit microcontroller includes the following tools: •...
Page 63 Flexible Peripheral Interconnect Buses (FPI Bus) for on-chip interconnections and its FPI Bus control unit (SBCU) • The System Timer (STM) with high-precision, long-range timing capabilities • The TC1784 includes a power management system, a watchdog timer as well as reset logic User´s Manual 1-24 V1.1, 2011-05...
Page 64: On-Chip Peripheral Units Of The Tc1784
The TC1784 microcontroller offers several versatile on-chip peripheral units such as serial controllers, timer units, and Analog-to-Digital converters. Several I/O lines on the TC1784 ports are reserved for these peripheral units to communicate with the external world. On-Chip Peripheral Units •...
Page 65 MCB05762_mod Figure 1-5 General Block Diagram of the ASC Interface The ASC provides serial communication between the TC1784 and other microcontrollers, microprocessors, or external peripherals. The ASC supports full-duplex asynchronous communication and half-duplex synchronous communication. In Synchronous Mode, data is transmitted or received synchronous to a shift clock that is generated by the ASC internally.
Page 66: High-Speed Synchronous Serial Interfaces (Ssc)
1.4.2 High-Speed Synchronous Serial Interfaces (SSC) The TC1784 includes three High-Speed Synchronous Serial Interfaces, SSC0, SSC1, and SSC2. All three SSC modules have the same functionality. Figure 1-6 shows a global view of the of the Synchronous Serial interface (SSC).
Page 67 TC1784 Introduction MRSTA MRSTB Master MTSR Clock MTSR Control MTSRA MTSRB Slave MRST MRST Address Decoder SCLKA Port Slave SCLKB Module Control (Kernel) SCLK Master SCLK SLSI[7:1] Interrupt Slave SLSI[7:1] SLSO[7:0] Control SLSO[7:0] SLSOANDO[7:0] Master SLSOANDO[7:0] SLSOANDI[7:0] DMA Requests Enable...
Page 68 TC1784 Introduction Features: • Master and Slave Mode operation – Full-duplex or half-duplex operation – Automatic pad control possible • Flexible data format – Programmable number of data bits: 2 to 16 data bits (with parity: 1 to 15 data bits) –...
Page 69: Micro Second Channel Interface (Msc)
Introduction 1.4.3 Micro Second Channel Interface (MSC) The TC1784 includes a Micro Second Channel interface, the MSC0. The Micro Second Channel (MSC) interface provides serial communication links typically used to connect power switches or other peripheral devices. The serial communication link includes a fast synchronous downstream channel and a slow asynchronous upstream channel.
Page 70 TC1784 Introduction Features • Fast synchronous serial interface to connect power switches in particular, or other peripheral devices via serial buses • High-speed synchronous serial transmission on downstream channel – Serial output clock frequency: /2 ( = 90 MHz) MSCmax –...
Page 71: Flexray™ Protocol Controller (E-Ray)
Clock Output eray_overview_32.vsd Figure 1-8 General Block Diagram of the E-Ray Interface ® ® 1) Infineon , Infineon Technologies , are trademarks of Infineon Technologies AG. FlexRay™ is a trademark of FlexRay Consortium. User´s Manual 1-32 V1.1, 2011-05 Intro, V1.0...
Page 72 TC1784 Introduction The E-Ray module communicates with the external world via three I/O lines each channel. The RXDAx and RXDBx lines are the receive data input signals, TXDA and TXDB lines are the transmit output signals, TXENA and TXENB the transmit enable signals.
Page 73 TC1784 Introduction • Automatic delayed read access to Input Command Request Register (IBCR) if a data transfer from Input Shadow Buffer to Message RAM to (initiated by a previous write access to the IBCR) is ongoing. • Four Input Buffer for building up transmission Frames in parallel.
Page 74 TC1784 Introduction 1.4.5 MultiCAN Controller The MultiCAN module provides three independent CAN nodes, representing three serial communication interfaces. The number of available message objects is 128. C AN MultiCAN Module Kernel Clock C L C Control P9.1 / TXDC2 TXDCAN2...
Page 75 TC1784 Introduction Features • Compliant with ISO 11898 • CAN functionality according to CAN specification V2.0 B active • Dedicated control registers for each CAN node • Data transfer rates up to 1 Mbit/s • Flexible and powerful message transfer control and error handling capabilities •...
Page 76: Micro Link Interface (Mli)
– Module SRAMs with ECC protection 1.4.6 Micro Link Interface (MLI) The TC1784 contains one Micro Link Interface, MLI0. The Micro Link Interface (MLI) is a fast synchronous serial interface to exchange data between microcontrollers or other devices, such as stand-alone peripheral components.
Page 77 TC1784 Introduction • Programmable baud rates – MLI transmitter baud rate: max. /2 (= 45 Mbit/s @ 90 MHz module clock) – MLI receiver baud rate: max. • Address range protection scheme to block unauthorized accesses • Multiple receiving devices supported User´s Manual...
Page 78 TC1784 Introduction Figure 1-11 shows a general block diagram of the MLI module. TREADY[D:A] TVALID[D:A] Fract. TDATA Divider Transmitter Control TCLK TR[3:0] Port MLI Module Control BRKOUT RCLK[D:A] RREADY[D:A] Move SR[7:0] RVALID[D:A] Engine Receiver Control RDATA[D:A] MCB06062_mod Figure 1-11 General Block Diagram of the MLI Modules The MLI transmitter and MLI receiver communicate with other MLI receivers and MLI transmitters via a four-line serial connection each.
Page 79: General Purpose Timer Array (Intro)
TC1784 Introduction 1.4.7 General Purpose Timer Array (Intro) The TC1784 contains the General Purpose Timer Array (GPTA0), plus the additional Local Timer Cell Array (LTCA2). Figure 1-12 shows a global view of the GPTA modules. The GPTA provides a set of timer, compare, and capture functionalities that can be flexibly combined to form signal measurement and signal generation units.
Page 80: Functionality Of Gpta0
TC1784 Introduction 1.4.7.1 Functionality of GPTA0 The General Purpose Timer Array (GPTA0) provides a set of hardware modules required for high-speed digital signal processing: • Filter and Prescaler Cells (FPC) support input noise filtering and prescaler operation. • Phase Discrimination Logic units (PDL) decode the direction information output by a rotation tracking system.
Page 81 TC1784 Introduction – /4 maximum input signal frequency in 2-sensor Mode, /6 maximum input GPTA GPTA signal frequency in 3-sensor Mode • Duty Cycle Measurement (DCM) – Four independent units – 0 - 100% margin and time-out handling – maximum resolution GPTA –...
Page 82: Functionality Of Ltca2
TC1784 Introduction On-chip Trigger Unit • 16 on-chip trigger signals I/O Sharing Unit • Interconnecting inputs and outputs from internal clocks, FPC, GTC, LTC, ports, and MSC interface 1.4.7.2 Functionality of LTCA2 The Local Timer Cell Array (LTCA2) provides a set of hardware modules required for high-speed digital signal processing: •...
Page 83: Analog-To-Digital Converters
TC1784 Introduction 1.4.8 Analog-to-Digital Converters The TC1784 includes two Analog to Digital Converter modules (ADC0, ADC1) and one Fast Analog to Digital Converter (FADC). 1.4.8.1 ADC Block Diagram The analog to digital converter module (ADC) allows the conversion of analog input values into discrete digital values based on the successive approximation method.
Page 84 TC1784 Introduction • and 1 alternative reference input at channel 0 AREF • Programmable sample time (in periods of f ADCI • Wide range of accepted analog clock frequencies f ADCI • Multiplexer test mode (channel 7 input can be connected to ground via a resistor for test purposes during run time by specific control bit) •...
Page 85: Fadc Short Description
TC1784 Introduction 1.4.8.2 FADC Short Description General Features • Extreme fast conversion, 21 cycles of clock (262.5 ns @ = 80 MHz) FADC FADC • 10-bit A/D conversion (higher resolution can be achieved by averaging of consecutive conversions in digital data reduction filter) •...
Page 86 FAREF FAGND Input Structure The input structure of the FADC in the TC1784 contains: • A differential analog input stage for each input channel to select the input impedance (differential or single-ended measurement) and to decouple the FADC input signal from the pins.
Page 87 FAIN0P DDMF conversion FAIN0N control Control gain SSMF CHNR FAIN2P DDMF FAIN2N SSMF FAIN1P DDMF FAIN1N DDAF SSAF SSMF FAIN3P DDMF FAIN3N SSMF MCA06432_m4n DDIF SSMF Figure 1-15 FADC Input Structure in TC1784 User´s Manual 1-48 V1.1, 2011-05 Intro, V1.0...
Page 88: External Bus Interface
TC1784 Introduction 1.4.9 External Bus Interface The External Bus Unit (EBU) of the TC1784 controls the accesses from peripheral units to external memories. Features: • 64-bit internal LMB interface • 16-bit external multiplexed bus interface – Support for 3.3 V Flash and 3.3 V SRAM memory devices.
Page 89: Real Time Trace
TC1784 Introduction • Central Suspend Switch to suspend parts of the system (TriCore, PCP, Peripherals) instead if breaking them as reaction to a debug event. • Dedicated interrupt resources to handle debug events inside TriCore (breakpoint trap, software interrupt) and Cerberus (can trigger PCP), e.g. for implementing Monitor programs.
Page 90: Tool Interfaces
Hardware-accelerated checksum calculation (e.g. for Flash content). • RAM tests optimized for the implemented architecture. 1.5.6 FAR Support To efficiently locate and identify faults after integration of a TC1784 into a system special functions are available: • Boundary Scan (IEEE 1149.1) via JTAG and DAP. •...
Page 91: Cpu Subsystem
TC1784 CPU Subsystem CPU Subsystem The TC1784 processor contains a TriCore 1.3.1 CPU. This chapter describes the implementation-specific options of the CPU, and should be read in conjunction with the TriCore Architecture Manual, which describes the complete TriCore Architecture including the register and instruction set.
Page 92: Central Processing Unit Features
TC1784 CPU Subsystem Central Processing Unit Features The 180 MHz TriCore TC1784 CPU includes: Architecture • 32-bit load store architecture • 4 Gbyte address range (2 • 16-bit and 32-bit instructions for reduced code size • Data types: – Boolean, integer with saturation, bit array, signed fraction, character, double-word integers, signed integer, unsigned integer, IEEE-754 single-precision floating point •...
Page 93: Cpu Diagram
TC1784 CPU Subsystem 2.2.1 CPU Diagram The Central Processing Unit (CPU) comprises of an Instruction Fetch Unit, an Execution Unit, a General Purpose Register File (GPR), a CPU Slave interface (CPS), and Floating Point Unit (FPU). To Program Memory Interface (PMI)
Page 94: Instruction Fetch Unit
TC1784 CPU Subsystem 2.2.2 Instruction Fetch Unit The Instruction Fetch Unit pre-fetches and aligns incoming instructions from the 64-bit wide Program Memory Interface (PMI). It contains an instruction pre-fetch buffer which may contain up to 128-bits of instructions linearly pre-fetched ahead of the current program counter.
Page 95: Execution Unit
TC1784 CPU Subsystem 2.2.3 Execution Unit The Execution Unit contains the Integer Pipeline, the Load/Store Pipeline and the Loop Pipeline. The Integer Pipeline and Load/Store Pipeline have four stages: Fetch, Decode, Execute, and Write-back. The Execute stage may extend beyond one cycle to accommodate multi-cycle operations such as load instructions.
Page 96: General Purpose Register File
TC1784 CPU Subsystem 2.2.4 General Purpose Register File The CPU has a General Purpose Register (GPR) file, divided into an Address Register File (registers A0 through A15) and a Data Register File (registers D0 through D15). The data flow for instructions issued to the Load/Store Pipeline is steered through the Address Register File.
Page 97: Cpu Implementation-Specific Features
TC1784 CPU Subsystem CPU Implementation-Specific Features This section describes the implementation-specific features of the CPU. For a complete description of all registers, refer to the TriCore Architecture Manual. 2.3.1 Context Save Areas Context Save Areas (CSA) may be placed in LDRAM or cached external memory.
Page 98 TC1784 CPU Subsystem The CPU must not perform Load/Store instructions to the mapped address of the PC in Segment 15. A MEM trap will be generated in such a case. Bit 0 of the PC register is read-only and hard-wired to 0.
Page 99: Interrupt System
TC1784 CPU Subsystem 2.3.3 Interrupt System An interrupt request can be generated by the on-chip peripheral units, or it can be generated by external events. Requests can be targeted to either the CPU, or to the Peripheral Control Processor (PCP).
Page 100: Memory Integrity Error Handling
TC1784 CPU Subsystem PIE Program Memory Integrity Error (TIN 5) The PIE trap is raised whenever an uncorrectable memory integrity error is detected in an instruction fetch from a local memory. The trap is synchronous to the erroneous instruction. The trap is of Class-4 and has a TIN of 5.
Page 101 TC1784 CPU Subsystem signals are passed to the core along with their corresponding instruction half-words. Whenever an attempt is made to issue an instruction containing an uncorrectable memory integrity error a synchronous PIE trap is raised. The trap handler is then responsible for correcting the memory entry and re-starting program execution.
Page 102: Data Side Memories
TC1784 CPU Subsystem For instruction fetch requests from the TriCore CPU to ICACHE, the program tag ECC bits are read along with the data bits and an error flag is computed. A way hit is triggered only if the tag address comparison succeeds, the valid bit is set and no ECC error in the associated tag way is detected, any other result is considered a miss.
Page 103 TC1784 CPU Subsystem For write operations to LDRAM of half-word size or greater, the ECC bits are pre- calculated and written to the memory in parallel with the data bits. For byte write operations the memory transaction is transformed into a half-word read-modify-write sequence inside the DMI module.
Page 104 TC1784 CPU Subsystem uncorrectable error in the associated tag way is detected, any other result is considered a miss. In the normal case where no error is detected in either tag way then the cache line is filled/refilled as normal. In the case of a cache miss where an error is detected in...
Page 105: Tricore 1.3 Compatibility
TC1784 CPU Subsystem 2.3.5.3 TriCore 1.3 Compatibility In order to allow code written for existing TriCore 1.3 based devices to be utilised without modification, a compatibility mode is included for both the program and data side memory integrity error handling. This compatibility mode is enabled by setting the COMPAT.PIE/DIE bit(s) to one.
Page 106: Cpu Subsystem Registers
TC1784 CPU Subsystem CPU Subsystem Registers This section describes the implementation-specific features of the CPU Subsystem registers listed in Table 1. For complete descriptions of all registers refer to the TriCore Architecture Manual. Table 1 CPU Subsystem Registers Registers Purpose...
Page 107: Cpu Core Special Function Registers (Csfr)
TC1784 CPU Subsystem CPU Core Special Function Registers (CSFR) Figure 6 shows the CSFR registers of the TC1784. Program State Context Stack Information Management Management Registers Registers Registers PCXI Compatibility System Control Interrupt & Trap Register Registers Control Registers COMPAT...
Page 108 TC1784 CPU Subsystem Table 2 Core Special Function Registers (cont’d) Short Description Offset Access Mode Reset Value Name Address Read Write Interrupt Stack Pointer FE28 U, SV, SV, E, Class 3 Reset Register 0000 0100 ICU Interrupt Control Register FE2C...
Page 109: Registers
TC1784 CPU Subsystem 2.5.1 Registers The implementation-specific Program Status Word Register (PSW) is an extension of the PSW description in the TriCore Architecture Manual. The status flags used for FPU operations overlay the status flags used for Arithmetic Logic Unit (ALU) operations.
Page 110 TC1784 CPU Subsystem Interrupt Control Register The Interrupt Control Register (ICR) is an implementation-specific CFSR. Its Arbitration Cycle Control implementation-specific details are defined in bits 24 to 26. Interrupt Control Register (F7E1 FE2C Reset Value: 0000 0000 CARBCYC PIPN CCPN...
Page 111 MMU is not available. All other bits of MMU_CON are undefined. Note: The MMU is not available in TC1784. Note: The non-shaded areas in the register description define the implementation- specific bits/bit fields. The shaded areas are defined in the TriCore Architecture Manual.
Page 112 TC1784 CPU Subsystem CPU Identification Register CPU_ID CPU Identification Register (F7E1 FE18 Reset Value: 000A C0XX MOD: 000A MOD_32B REV: xx Field Bits Type Description MOD_REV [7:0] Revision Number For version numbering. The value of the revision starts with 01...
Page 113 TC1784 CPU Subsystem Compatibility Control Register The Compatibility Control Register (COMPAT) is an implementation-specific CSFR which allows certain elements of backwards compatibility with TriCore 1.3 behaviour to be forced. The reset value of the COMPAT register ensures that backwards compatibility with TriCore 1.3 is enabled by default.
Page 114: Cpu General Purpose Registers
TC1784 CPU Subsystem CPU General Purpose Registers Figure 7 shows the General Purpose Registers (GPRs) of the TC1784. Address General Data General Purpose Registers Purpose Registers (AGPR) (DGPR) A15 (implicit address) D15 (implicit data) 64-bit Extended Data Registers A11 (return address)
Page 115 TC1784 CPU Subsystem Table 3 GPR Registers (cont’d) Short Description Offset Access Mode Reset Name Address Read Write Data Register 5 FF14 U, SV, Class 3 Reset XXXX XXXX Data Register 6 FF18 U, SV, Class 3 Reset XXXX XXXX...
Page 116 TC1784 CPU Subsystem Table 3 GPR Registers (cont’d) Short Description Offset Access Mode Reset Name Address Read Write Address Register 5 FF94 U, SV, Class 3 Reset XXXX XXXX Address Register 6 FF98 U, SV, Class 3 Reset XXXX XXXX...
Page 117: Cpu Memory Protection Registers
As shown in Figure 8, there are four Memory Protection Register Sets in the TC1784. The sets specify memory protection ranges and permissions for code and data. The PSW.PRS bit field determines which of these sets is currently in use by the CPU. The Memory Protection Registers are Core Special Function Registers, they are described in detail in the TriCore Architecture Manual.
Page 118 TC1784 CPU Subsystem Table 4 Memory Protection Registers Short Description Offset Access Mode Reset Name Address Read Write DPR0_0L Data Segment Protection C000 U, SV, Class 3 Reset Register Set 0, Range 0, 0000 0000 Lower Boundary DPR0_0U Data Segment Protection...
Page 119 TC1784 CPU Subsystem Table 4 Memory Protection Registers (cont’d) Short Description Offset Access Mode Reset Name Address Read Write DPR1_1U Data Segment Protection C40C U, SV, Class 3 Reset Register Set 1, Range 1, 0000 0000 Upper Boundary DPR1_2L Data Segment Protection...
Page 120 TC1784 CPU Subsystem Table 4 Memory Protection Registers (cont’d) Short Description Offset Access Mode Reset Name Address Read Write DPR2_3L Data Segment Protection C818 U, SV, Class 3 Reset Register Set 2, Range 3, 0000 0000 Lower Boundary DPR2_3U Data Segment Protection...
Page 121 TC1784 CPU Subsystem Table 4 Memory Protection Registers (cont’d) Short Description Offset Access Mode Reset Name Address Read Write CPR0_0U Code Segment Protection D004 U, SV, Class 3 Reset Register Set 0, Range 0, 0000 0000 Upper Boundary CPR0_1L Code Segment Protection...
Page 122 TC1784 CPU Subsystem Table 4 Memory Protection Registers (cont’d) Short Description Offset Access Mode Reset Name Address Read Write CPR3_0L Code Segment Protection DC00 U, SV, Class 3 Reset Register Set 3, Range 0, 0000 0000 Lower Boundary CPR3_0U Code Segment Protection...
Page 123: Fpu Registers
TC1784 CPU Subsystem FPU Registers A number of FPU Special Function Registers (CSFRs) have been introduced to the TriCore 1.3.1 architecture in order to fully support functional enhancements. FPU Trap Registers FPU_TRAP_CON FPU_TRAP_PC FPU_TRAP_OPC FPU_TRAP_SRCn MCA06073_2 Figure 9 TriCore 1.3.1 CSFR Registers...
Page 124: Registers
TC1784 CPU Subsystem 2.8.1 Registers FPU Identification Register FPU_ID Trapping Identification Register (F7E1 A020 Reset Value: 0054 C003 MOD: 0054 MOD_32B REV: xx Field Bits Type Description MOD_REV [7:0] Revision Number For version numbering. The value of the revision starts with 01...
Page 125: Memory Integrity Registers
TC1784 CPU Subsystem Memory Integrity Registers Memory Integrity Registers (CSFRs). Integrity Registers MIECON CCPIER CCDIER PIEAR PIETR DIEAR DIETR SMACON MCA06073-3 Figure 2-1 TriCore 1.3.1 CSFR Registers Table 2-1 Memory Integrity Registers Short Description Offset Access Mode Reset Name Address...
Page 126 TC1784 CPU Subsystem Table 2-1 Memory (cont’d) Integrity Registers Short Description Offset Access Mode Reset Name Address Read Write DIETR Data Integrity Error Trap 9024 U, SV, Class 3 Reset Register 0000 0000 SMACON SIST Mode Access Control 900C U, SV,...
Page 127: Register Descriptions
TC1784 CPU Subsystem 2.9.1 Register Descriptions Memory Integrity Error Control Register The Memory Integrity Error Control Register (MIECON) allows software to control the handling of uncorrectable memory integrity errors. MIECON Memory Integrity Error Control Register (F7E1 9044 Reset Value: 0000 0000...
Page 128 TC1784 CPU Subsystem Field Bits Type Description DTIEE Data Tag Integrity Error Enable Enables handling of uncorrectable integrity errors for the Data Tag. Uncorrectable integrity error handling disabled - all memory accesses interpreted as error free. Uncorrectable integrity error handling enabled.
Page 129 TC1784 CPU Subsystem Memory Integrity Error Control Register 2 The Memory Integrity Error Control Register 2 (MIECON2) allows software to control the handling of correctable memory integrity errors. The behaviour of MIECON2 is configured according to the tc_cfg_sec_con_en_i input to the TriCore1.3.1 core.
Page 130 TC1784 CPU Subsystem Function Although the xxIEE and xxSECE bits for a given memory type exist in different registers (MIECON and MIECON2 respectively) due to different protection requirements for these CSFR bits, the bits interact to perform the following general functions.
Page 131 TC1784 CPU Subsystem Program Integrity Error Information Registers Two architecturally visible registers (PIETR, PIEAR) allow software to localise the source of the last detected uncorrectable program memory integrity error. These registers are updated when an uncorrectable program integrity error condition is detected and the PIETR.IED bit is zero.
Page 132 TC1784 CPU Subsystem Program Integrity Error Trap Register (PIETR) PIETR Program Integrity Error Trap Register (F7E1 9214 Reset Value: 0000 0000 BUS_ID IE_B IE_S IE_C IE_T IED Field Bits Type Description Integrity Error Detected Read Operation: No program integrity error condition occurred.
Page 133 TC1784 CPU Subsystem Program Integrity Error Address Register This register contains the physical address accessed by the operation that encountered a uncorrectable program memory integrity error. This register is only updated if PIETR.IED is zero. PIEAR Program Integrity Error Address Register...
Page 134 TC1784 CPU Subsystem Data Integrity Error Information Registers Two architecturally visible registers (DIETR, DIEAR) allow software to localise the source of the last detected uncorrectable data memory integrity error. These registers are updated when an uncorrectable data integrity error condition is detected and the DIETR.IED bit is zero.
Page 135 TC1784 CPU Subsystem Data Integrity Error Trap Register (DIETR) DIETR Data Integrity Error Trap Register (F7E1 9024 Reset Value: 0000 0000 BUS_ID IE_B IE_S IE_C IE_T IED Field Bits Type Description Integrity Error Detected Read Operation: No data integrity error condition occurred.
Page 136 TC1784 CPU Subsystem Field Bits Type Description [31:10] Reserved Read as 0; should be written with 0. User´s Manual 2-46 V1.1, 2011-05 CPU, V3.03...
Page 137 TC1784 CPU Subsystem Data Integrity Error Address Register This register contains the physical address accessed by the operation that encountered a uncorrectable data memory integrity error. This register is only updated if DIETR.IED is zero. DIEAR Data Integrity Error Address Register...
Page 138 TC1784 CPU Subsystem SIST (Software In-System) Test Support The TriCore 1.3.1 core protects against memory integrity errors by ECC protection of the on-core memories. This has the side-effect of requiring memory blocks wider than the normal data access path to the memory. The additional ECC storage bits are not easily accessible via the existing data paths, causing problems where SIST based testing of the memories is required.
Page 139 TC1784 CPU Subsystem Field Bits Type Description [1:0] Instruction Cache Memory SIST Mode Access control Normal Operation, No Mapping. Instruction cache memory configured as program SPR. [3:2] Program Tag Memory SIST Mode Access Control Normal Operation, No Mapping. Data Array Mapping, no error detection/correction.
Page 140 TC1784 CPU Subsystem Field Bits Type Description [13:12] Data Scratch Memory SIST Mode Access Control Normal Operation, No Mapping, Performance Optimised. Data Array Mapping, no error detection/correction. Check Array Mapping, no error detection/correction. Data Array Mapping, error detection/correction enabled. IODT...
Page 141 TC1784 CPU Subsystem Control Fields The control fields within the SMACON register allow individual control of the local memories. Each memory may be mapped to operate in a number of different modes. Normal operation, No Mapping No mapping of the memories is performed and normal operation is possible. Embedded memories not usually directly addressable are not accessible in the system address map.
Page 142: Cpu Slave Interface (Cps) Registers
TC1784 CPU Subsystem 2.10 CPU Slave Interface (CPS) Registers The CPU Slave Interface (CPS) of the TriCore CPU directly accesses the interrupt service request registers in the CPU from the System Peripheral Bus. The CPS registers are described in detail in the TriCore Architecture Manual.
Page 143: Register Descriptions
TC1784 CPU Subsystem 2.10.1 Register Descriptions This registers have a specific implementation detail, the Type of Service Control (TOS) bit/bit field. CPU Service Request Control Register CPU_SRCn (n = 0-3) CPU Service Request Control Register n (F7E0 FFFC -n*4) Reset Value: 0000 0000...
Page 144 TC1784 CPU Subsystem CPS Module Identification Register CPS_ID CPS Module Identification Register (F7E0 FF08 Reset Value: 0015 C0XX MOD: 0015 MOD_32B REV: xx Field Bits Type Description MOD_REV [7:0] Revision Number For version numbering. The value of the revision starts with 01...
Page 145 TC1784 CPU Subsystem CPU Software Breakpoint Service Request Control Register CPU_SBSRC CPU Software Breakpoint Service Request Control Register (F7E0 FFBC Reset Value: 0000 0000 SRR SRE SRPN Field Bits Type Description Type of Service Control Service Provider = CPU Reserved Reserved Read as 0;...
Page 146: Core Debug Registers
TC1784 CPU Subsystem 2.11 Core Debug Registers The Core Debug registers are available for debug purposes. For a complete description of all registers, refer to the TriCore Architecture Manual. Performance Core Debug Counter Registers Registers CCTRL DBGSR CCNT EXEVT ICNT...
Page 147 TC1784 CPU Subsystem Table 8 Core Debug Registers (cont’d) Short Description Offset Access Mode Reset Name Address Read Write EXEVT External Break Input Event FD08 U, SV, SV, 32 Class 1 Reset Register 0000 0000 CREVT Core SFR Access Break...
Page 148: Implementation Specific Reset Values
TC1784 CPU Subsystem 2.12 Implementation Specific Reset Values This section summarizes the implementation specific reset values of the CPU registers not defined in this chapter. Table 9 Implementation Specific Reset Values Register Address Reset Value PCXI F7E1 FE00 0000 0000...
Page 149: Cpu Instruction Timing
TC1784 CPU Subsystem 2.13 CPU Instruction Timing This section gives information on CPU instruction timing by execution unit. The Integer Pipeline and Load/Store Pipeline are always present, and the Floating Point Unit (FPU) is optional. The Load/Store unit implements the optional TLB instructions.
Page 150: Integer-Pipeline Instructions
TC1784 CPU Subsystem 2.13.1 Integer-Pipeline Instructions These are the Integer-Pipeline instruction timings for each instruction. 2.13.1.1 Simple Arithmetic Instruction Timings Each instruction is single issued. Table 10 Simple Arithmetic Instruction Timing Instruction Result Repeat Instruction Result Repeat Latency Rate Latency...
Page 151 TC1784 CPU Subsystem Table 10 Simple Arithmetic Instruction Timing (cont’d) Instruction Result Repeat Instruction Result Repeat Latency Rate Latency Rate CSUB SUBS.H CSUBN SUBS.HU SUBS.U MAX.B SUBX MAX.BU Compare Instructions LT.B EQ.B LT.BU EQ.H LT.H EQ.W LT.HU EQANY.B LT.U EQANY.H LT.W...
Page 152 TC1784 CPU Subsystem Table 10 Simple Arithmetic Instruction Timing (cont’d) Instruction Result Repeat Instruction Result Repeat Latency Rate Latency Rate AND.GE.U OR.NE AND.LT OR.NOR.T AND.LT.U OR.OR.T AND.NE OR.T AND.NOR.T AND.OR.T ORN.T AND.T XNOR ANDN XNOR.T ANDN.T NAND XOR.EQ NAND.T XOR.GE XOR.GE.U...
Page 153 TC1784 CPU Subsystem Table 10 Simple Arithmetic Instruction Timing (cont’d) Instruction Result Repeat Instruction Result Repeat Latency Rate Latency Rate SH.NAND.T Coprocessor 0 Instructions BMERGE DVSTEP BSPLIT DVSTEP.U DVADJ IXMAX DVINIT IXMAX.U DVINIT.U IXMIN DVINIT.B IXMIN.U DVINIT.H PACK DVINIT.BU PARITY DVINIT.HU...
Page 154: Multiply Instruction Timings
TC1784 CPU Subsystem 2.13.1.2 Multiply Instruction Timings Each instruction is single issued. Table 11 Multiply Instruction Timing Instruction Result Repeat Instruction Result Repeat Latency Rate Latency Rate MUL.Q MUL.U MULM.H MULS MULR.H MULS.U MULR.Q MUL.H User´s Manual 2-64 V1.1, 2011-05...
Page 155: Multiply Accumulate (Mac) Instruction Timing
TC1784 CPU Subsystem 2.13.1.3 Multiply Accumulate (MAC) Instruction Timing Each instruction is single issued. Table 12 Multiply Accumulate Instruction Timing Instruction Result Repeat Instruction Result Repeat Latency Rate Latency Rate MADD MSUB MADD.U MSUB.U MADDS MSUBS MADDS.U MSUBS.U MADD.H MSUB.H MADD.Q...
Page 156: Control Flow Instruction Timing
TC1784 CPU Subsystem 2.13.1.4 Control Flow Instruction Timing Note all Integer Pipeline Control flow instructions are conditional. • Each instruction is single issued. • All target locations yield a full instruction in one access (i.e. not 16-bits of a 32-bit instruction).
Page 157: Load-Store Pipeline Instructions
TC1784 CPU Subsystem 2.13.2 Load-Store Pipeline Instructions This section summarizes the Load-Store Pipeline instructions. 2.13.2.1 Address Arithmetic Timing Each instruction is single issued. Table 14 Address Arithmetic Instruction Timing Instruction Result Repeat Instruction Result Repeat Latency Rate Latency Rate Load Store Arithmetic Instructions ADD.A...
Page 158: Control Flow Instruction Timing
TC1784 CPU Subsystem 2.13.2.2 Control Flow Instruction Timing This section summarizes the timing of Control Flow instructions. Each instruction is single issued. • All targets yield a full instruction in one access (not 16-bits of a 32-bit instruction). • All code fetches take a single cycle. Timing is best case; no cache misses for context operations, no pending stores.
Page 159: Load Instruction Timing
TC1784 CPU Subsystem For JLI, JEQ.A, JNE.A JNZ.A, JZ.A Instructions: Flow Latency Repeat Rate Correctly predicted, not taken Correctly predicted, taken Wrongly predicted 2.13.2.3 Load Instruction Timing Load instructions can produce two results if they use the pre-increment, post-increment, circular or bit-reverse addressing modes. Hence, in those cases there are two latencies that must be specified, the result latency for the value loaded from memory and the address latency for using the updated address register result.
Page 160: Store Instruction Timing
TC1784 CPU Subsystem 2.13.2.4 Store Instruction Timing Cache and Store instructions similar to Load instructions will have a result for the pre- increment, post-increment, circular or bit-reverse addressing modes, but do not produce a ‘memory’ result. • Each instruction is single issued.
Page 161: Floating Point Pipeline Timing
TC1784 CPU Subsystem 2.13.3 Floating Point Pipeline Timing These instructions are only valid if the optional Floating Point Unit is implemented. Each instruction is single issued. Table 18 Floating Point Instruction Timing Instruction Result Repeat Instruction Result Repeat Latency Rate...
Page 162: Program Memory Interface (Pmi)
TC1784 CPU Subsystem 2.14 Program Memory Interface (PMI) Figure 12 shows the block diagram of the Program Memory Interface (PMI) of the TC1784. Program Memory Interface (PMI) To/From PMEM Data Switch ICACHE & Data Alignment & Interface Control SPRAM Control...
Page 163: Lmb Access Priorities
5. PMI 6. DMA Low 2.14.3 Scratchpad RAM The TC1784 contains up to 40 Kbyte of scratchpad RAM. Scratchpad RAM provides a fast, deterministic program fetch access from the CPU for use by performance critical code sequences. • CPU program fetch accesses to scratchpad RAM are never cached in the instruction cache and are always directly targeted to the scratchpad RAM.
Page 164: Instruction Cache
The scratchpad RAM may also be accessed from the LMB Slave interface by another bus master, such as the Data Memory Interface (DMI). The scratchpad RAM may be both read and written from the LMB. In the TC1784, the PMI LMB Slave interface supports all LMB transaction types.
Page 165: Program Line Buffer
TC1784 CPU Subsystem Instruction Cache Bypass The Instruction Cache may be bypassed, under control of PMI_CON0.PCBYP, to provide a direct instruction fetch path for the CPU Fetch Unit. The default value of PMI_CON0.PCBYP is such that the ICACHE is bypassed after reset. ICACHE bypass should be disabled during initialization to enable the ICACHE.
Page 166: Pmi Registers
TC1784 CPU Subsystem 2.14.6 PMI Registers Three control registers are implemented in the Program Memory Interface. These registers and their bits are described in this section. PMI Control Registers PMI_CON0 PMI_CON1 PMI_CON2 PMI_STR MCA06079-1 Figure 13 PMI Registers Table 19...
Page 167: Pmi Register Descriptions
TC1784 CPU Subsystem 2.14.6.1 PMI Register Descriptions PMI Control Register 0 PMI_CON0 PMI Control Register 0 (F87F FD10 Reset Value: 0000 0002 Field Bits Type Description PCBYP Instruction Cache Bypass Cache enabled Cache bypassed (disabled) [31:2], Reserved Read as 0; should be written with 0.
Page 168 TC1784 CPU Subsystem PMI Control Register 1 PMI_CON1 PMI Control Register 1 (F87F FD14 Reset Value: 0000 0000 Field Bits Type Description PCINV Instruction Cache Invalidate Write Operation: No effect. Normal instruction cache operation. Initiate invalidation of entire instruction cache.
Page 169 TC1784 CPU Subsystem PMI Control Register 2 The PMI_CON2 register may only be written in supervisor mode and is endinit protected. In addition write accesses to PMI_CON2 are also dependent on the status of Flash read protection. Whenever Flash read protection is inactive PMI_CON2 may be written as often as required (bearing in mind operational constraints for changing SRAM and cache sizes).
Page 170 TC1784 CPU Subsystem Field Bits Type Description PC_SZ_CFG [19:16] rwh Instruction Cache Size Configuration Configuration of the Instruction Cache Size. Any program memory not utilised as instruction cache is configured as SPRAM. After reset this field is set to zero. This field may subsequently be written to select...
Page 171 TC1784 CPU Subsystem Program Memory Interface Synchronous Trap Register (PMI_STR) PMI_STR PMI Synchronous Trap Register (F87F FD20 Reset Value: 0000 0000 Field Bits Type Description FRESTF Fetch Range Error Synchronous Trap Flag FBESTF Fetch Bus Error Synchronous Trap Flag FPESTF...
Page 172 TC1784 CPU Subsystem PMI Identification Register PMI_ID PMI Identification Register (F87F FD08 Reset Value: 000B C0XX MOD: 000B MOD_32B REV: xx Field Bits Type Description MOD_REV [7:0] Revision Number For version numbering. The value of the revision starts with 01...
Page 173: Data Memory Interface (Dmi)
TC1784 CPU Subsystem 2.15 Data Memory Interface (DMI) This figure shows the block diagram of the Data Memory Interface (DMI) of the TC1784. Data Memory Interface (DMI) Data Switch DMEM & Data Alignment DCache & Interface Control LDRAM Control Registers...
Page 174: Lmb Access Priorities
2.15.4 Data Cache The TC1784 contains up to 4 KByte of Data Cache (DCache). The DCache is a two-way set-associative cache with a Least-Recently-Used (LRU) replacement algorithm, and is organised as 256 cache lines, with 128-bits per line. Associated with each DCache line is a single valid bit which pertains to the entire line.
Page 175: Data Line Buffer
The TC1784 data cache is of the writeback type. When the CPU writes to a cacheable location the data is merged with the corresponding cache line and not written to main memory immediately.
Page 176: Dmi Trap Generation
TC1784 CPU Subsystem A single valid bit is associated with the DLB, denoting that the DLB contents are valid. As such all accesses updating the DLB, whether data cache is configured or not, are implemented as LMB Burst Transfer 2 (BTR2) transactions, with the critical double-word of the DLB line being fetched first size.
Page 177 TC1784 CPU Subsystem Cache Writeback Error Cache writeback errors are detected when a data cache or DLB writeback sequence, initiated by a CPU load-store access generating a cache miss, encounters a bus error on the LMB. Note that unlike other error types, the address causing a cache writeback error is not related to the address of the CPU load-store access which caused the writeback.
Page 178: Dmi Registers
TC1784 CPU Subsystem 2.15.7 DMI Registers Two Control Registers and two Trap Flag registers are implemented in the DMI. These registers and their bits are described in this section. Control Registers Trap Flag Registers DMI_CON DMI_STR DMI_ID DMI_ATR MCA06081 Figure 15...
Page 179: Dmi Register Descriptions
TC1784 CPU Subsystem 2.15.7.1 DMI Register Descriptions DMI Control Register The DMI control register indicates the DMI data memory size and data cache availability. DMI_CON DMI Control Register (F87F FC10 Reset Value: 0800 0802 DMEM_SZ_CFG DC_SZ_CFG DMEM_SZ_AV DC_SZ_AV Field Bits...
Page 180 TC1784 CPU Subsystem Field Bits Type Description DMEM_SZ_CF [31:20] rwh Data Memory Size Configuration Configuration of the Data Memory (DMEM) size. After reset this field is set to equal the maximum DMEM size available, DMEM_SZ_AV. This field may subsequently be written to force a smaller DMEM size to be visible to software .
Page 181 TC1784 CPU Subsystem DMI Synchronous Trap Flag Register The DMI Synchronous Trap Flag Register, DMI_STR, holds the flags that identify the root cause of a Data-access Synchronous Bus Error (DSE). Reading DMI_STR in supervisor mode returns the register contents and then clears its contents. Reading DMI_STR in user mode returns the contents of the register but does not clear its contents.
Page 182 TC1784 CPU Subsystem DMI Asynchronous Trap Flag Register The DMI Asynchronous Trap Flag Register, DMI_ATR, holds the flags that inform about the root cause of a Data Access Asynchronous Bus Error (ASE). Reading DMI_ATR in supervisor mode returns the register contents and then clears its contents. Reading DMI_ATR in user mode returns the contents of the register but does not clear its contents.
Page 183 TC1784 CPU Subsystem DMI Identification Register DMI_ID DMI Identification Register (F87F FC08 Reset Value: 0008 C0XX MOD: 0008 MOD_32B REV: xx Field Bits Type Description MOD_REV [7:0] Revision Number For version numbering. The value of the revision starts with 01...
Page 184: System Control Unit (Scu)
TC1784 System Control Unit (SCU) System Control Unit (SCU) The System Control Unit (SCU) of the TC1784 handles all system control tasks beside the debug related tasks which are controlled by the OCDS/Cerberus. The SCU contains the following functional sub-blocks: •...
Page 185: Clock System Overview
TC1784 System Control Unit (SCU) Clock System Overview This section describes the TC1784 clock system. Topics covered include clock generation and the operation of clock circuitry. The TC1784 clock system provides the following functions: • Acquires and buffers incoming clock signals to create a master clock frequency •...
Page 186 SSC2 EXTCLK0 ADC0 R EFC L K1 MCDS ADC1 R EFC L K2 FADC ERAY Domain ERAY MLI0 PCP2 Domain PC P L MB PCP2 Toplevel _clock_1784 . Figure 3-1 TC1784 Clocking System User´s Manual V1.1, 2011-05 32-bit SCU, V1.18...
Page 187: Clock Generation Unit
System Control Unit (SCU) 3.1.1 Clock Generation Unit The Clock Generation Unit (CGU) allows a very flexible clock generation for the TC1784. During user program execution the frequency can be programmed for an optimal ratio between performance and power consumption.
Page 188: Oscillator Circuit (Osc)
XTAL1 Signal XTAL2 ext_clk_inl_mode Figure 3-3 TC1784 Direct Clock Input External Crystal / Ceramic Resonator Mode Figure 3-4 shows the recommended external circuitries for both operating modes, External Crystal / Ceramic Resonator Mode with and without external components. User´s Manual V1.1, 2011-05...
Page 189 TC1784 System Control Unit (SCU) XTAL1 XTAL1 XTAL2 XTAL2 without external Components with external Components ext_crystal _ mode Figure 3-4 External Circuitry for Crystal / Ceramic Resonator operation When using an external crystal / ceramic resonator, its frequency can be within the allowed range (the values are listed in the Data Sheet).
Page 190: Phase-Locked Loop (Pll) Module
TC1784 System Control Unit (SCU) 3.1.1.3 Phase-Locked Loop (PLL) Module The PLL can convert a low-frequency external clock signal to a high-speed internal clock for maximum performance. The PLL also has fail-safe logic that detects degenerate external clock behavior such as abnormal frequency deviations or a total loss of the external clock.
Page 191 TC1784 System Control Unit (SCU) Divider Divider Divider Lock- Detection Divider PLL_block Figure 3-5 PLL Block Diagram Clock Source Control The PLL clock is generated from in one of three software selectable modes: • Normal Mode • Prescaler Mode •...
Page 192 TC1784 System Control Unit (SCU) The output frequency is given by (3.2) f OSC ------------- - f PLL Freerunning Mode In Freerunning Mode the base frequency output of the Voltage Controlled Oscillator (VCO) is only divided down by a factor K2.
Page 193 TC1784 System Control Unit (SCU) clears all three bits OSCCON.PLLSP, OSCCON.PLLLV, and OSCCON.PLLHV all three trap status flags will be set. Therefore all three flags should be cleared before the trap generation is enabled again. The trap disabling-clearing-enabling sequence should also be used if only bit OSCCON.OSCRES is set without any modification of...
Page 194 TC1784 System Control Unit (SCU) Operation on the Freerunning Mode does not require an input clock frequency of The Freerunning Mode is automatically entered on a PLL VCO Loss-of-Lock event if bit PLLCON0.OSCDISCDIS is cleared. This mechanism allows a fail-safe operation of the PLL as in emergency cases still a clock is available.
Page 195 TC1784 System Control Unit (SCU) • PLLSTAT.VCOBYST = 1 • OSCCON.PLLLV = 1 Operation on the Prescaler Mode does require an input clock frequency of Therefore it is recommended to check and monitor if an input frequency is available at all by checking OSCCON.PLLLV. For a better monitoring also the upper frequency can be monitored via OSCCON.PLLHV.
Page 196 TC1784 System Control Unit (SCU) PLLSTAT . FINDIS Divider Divider Lock Detect. Osc. Divider PLLCON 0. VCOBYP PLL Block PLL_Normal_Mode. vsd Figure 3-8 PLL Normal Mode Diagram The output frequency is given by: (3.7) ⋅ -------------- - f f PLL ⋅...
Page 197 TC1784 System Control Unit (SCU) of the K2-divider has no impact on the VCO Lock status but still changes the PLL output frequency. Note: Changing the system operation frequency by changing the value of the K2-Divider has a direct coupling to the power consumption of the device. Therefore this has to be done carefully.
Page 198: Eray Phase-Locked Loop (Pll_Eray) Module
TC1784 System Control Unit (SCU) The PLL has a lock detection that supervises the VCO part of the PLL in order to differentiate between stable and instable VCO circuit behavior. The lock detector marks the VCO circuit and therefore the output of the VCO as instable if the two inputs differ too much.
Page 199 TC1784 System Control Unit (SCU) • VCO lock detection • 6-bit feedback divider N: (multiply by NDIV+1) • 5-bit output divider K1 or K2: (divide by either by K1DIV+1 or K2DIV+1) • Different operating modes – Prescaler Mode – Freerunning Mode –...
Page 200 TC1784 System Control Unit (SCU) PLL_ERAY Block K1- Divider PLL_ERAY K2- Divider Lock- Detection Divider PLLERAY _block Figure 3-9 PLL_ERAY Block Diagram Clock Source Control The PLL_ERAY clock is generated from in one of three software selectable PLL_ERAY modes: •...
Page 201 TC1784 System Control Unit (SCU) In Prescaler Mode the reference frequency is only divided down by a factor K1. The output frequency is given by (3.9) f OSC ------------- - f PLL Freerunning Mode In Freerunning Mode the base frequency output of the Voltage Controlled Oscillator (VCO) is only divided down by a factor K2.
Page 202 TC1784 System Control Unit (SCU) The output frequency is given by (3.11) f VCObase -------------------------- - f PLL The Freerunning Mode is selected by the following settings • PLLERAYCON0.VCOBYP = 0 • PLLERAYCON0.SETFINDIS = 1 The Freerunning Mode is entered when •...
Page 203 TC1784 System Control Unit (SCU) Divider PLL_ERAY PLLERAY CON0. VCOBY P PLL_ERAY Block PLLERAY _N_Prescaler _Mode. vsd Figure 3-11 PLL_ERAY Prescaler Mode Diagram The output frequency is given by: (3.12) f OSC ------------- - f PLL The Prescaler Mode is selected by the following settings •...
Page 204 TC1784 System Control Unit (SCU) The Prescaler Mode is requested from the Freerunning or Normal Mode by setting bit PLLERAYCON.VCOBYP. The Prescaler Mode is entered when the status bit PLLERAYSTAT.VCOBYST is set. Before the Prescaler Mode is requested the K1-...
Page 205 TC1784 System Control Unit (SCU) • PLLERAYSTAT.VCOBYST = 0 • PLLERAYSTAT.VCOLOCK = 1 • OSCCON.PLLLV = 1 • OSCCON.PLLHV = 1 Operation on the Normal Mode does require an input clock frequency of . Therefore it is recommended to check and monitor if an input frequency is available at all by checking OSCCON.PLLLV.
Page 206: Clock Control Unit
TC1784 System Control Unit (SCU) Depending on the selected divider value of the K2-Divider the duty cycle of the clock is selected. This can have an impact for the operation with an external communication interface. The duty cycles values for the different K2-divider values are defined in the Data Sheet.
Page 207 CCU_block . Figure 3-13 Clock Control Unit The clocking system of the TC1784 consists of the Clock Control Unit (CCU) and the Clock Generation Unit. There is also a fix reference clock REFCLK1 for the MCDS block which divides the master clock by 24.
Page 208: External Clock Output
TC1784 System Control Unit (SCU) 3.1.1.6 External Clock Output Two external clock outputs are provided via pins EXTCLK0 and EXTCLK1. These external clocks can be enabled/disabled via bits EXTCON.EN0 for EXTCLK0 and EXTCON.EN1 for EXTCLK1. Each of the clocks that defines a clock domain can individually be selected to be seen at pins EXTCLK0 or EXTCLK1, this is configured via bit field EXTCON.SEL0/1.
Page 209 TC1784 System Control Unit (SCU) EXTCON.SEL0 Fractional Divider EXTCON.EN0 Reserved Reserved Reserved P1.12 Reserved Reserved P2.8 PLL _ERAY EXTCON. GPTAINSEL Reserved Reserved Reserved GPTA [IN0] Reserved Reserved Reserved ERAY extclk . Figure 3-14 EXTCLK0 Generation Overview The fractional divider makes it possible to generate a external clock from the FPI-Bus clock using a programmable divider.
Page 210 TC1784 System Control Unit (SCU) STEP (10-bit) Fractional Divider Adder & RESULT (10-bit) Enable reset external divider external clock enable Control MC B0 5 6 0 4 m Figure 3-15 Fractional Divider Block Diagram The adder logic of the fractional divider can be configured for two operating modes: •...
Page 211 TC1784 System Control Unit (SCU) The output frequencies in Normal Divider Mode are defined according to the following formulas: × -- - (3.14) ------------------ - , with n = 1024 - STEP In order to get /2 STEP must be programmed with 3FF Fractional Divider Mode When the Fractional Divider Mode is selected (FDR.DM = 10...
Page 212 TC1784 System Control Unit (SCU) EXTCON.SEL1 EXTCON.DIV1 Reserved Reserved Reserved Reserved EXTCON.EN1 Reserved PLL_ERAY P1.0 Reserved Reserved EXTCON.NSEL Reserved Reserved Reserved Reserved Reserved extclk . Figure 3-16 EXTCLK1 Generation Clock is generated via a counter, so the output frequency can be selected in small steps.
Page 213: Cgu Registers
TC1784 System Control Unit (SCU) 3.1.1.7 CGU Registers System Oscillator Register This register controls the settings of OSC. OSCCON OSC Control Register (010 Reset Value: 0000 021A OSCVAL MODE GAINSEL Field Bits Type Description PLLLV Oscillator for PLL Valid Low Status Bit This bit indicates if the frequency output of OSC is usable for the VCO part of the PLL.
Page 214 TC1784 System Control Unit (SCU) Field Bits Type Description MODE [6:5] Oscillator Mode This bit field defines which mode can be used and if the oscillator entered the Power-Saving Mode or not. External Crystal Mode and External Input Clock Mode. The oscillator Power-Saving Mode is not entered.
Page 215 TC1784 System Control Unit (SCU) Field Bits Type Description OSCVAL [20:16] rw OSC Frequency Value This bit field defines the divider value that generates the reference clock that is supervised by the oscillator watchdog. is divided by OSCVAL + 1...
Page 216 TC1784 System Control Unit (SCU) Field Bits Type Description VCOLOCK PLL VCO Lock Status The frequency difference of greater than allowed. The VCO part of the PLL can not lock on a target frequency. The frequency difference of small enough to enable a stable VCO operation.
Page 217 TC1784 System Control Unit (SCU) Field Bits Type Description K2RDY K2 Divider Ready Status This bit indicates if the K2-divider operates on the configured value or not. this is of interest if the values is changed. K2-Divider is not ready to operate with the new...
Page 218 TC1784 System Control Unit (SCU) Field Bits Type Description SETFINDIS Set Status Bit PLLSTAT.FINDIS Bit PLLSTAT.FINDIS is left unchanged Bit PLLSTAT.FINDIS is set. The input clock from the oscillator is disconnected from the VCO part. CLRFINDIS Clear Status Bit PLLSTAT.FINDIS Bit PLLSTAT.FINDIS is left unchanged...
Page 219 TC1784 System Control Unit (SCU) PLLCON1 PLL Configuration 1 Register (01C Reset Value: 0002 000F K1DIV K2DIV Field Bits Type Description K2DIV [6:0] K2-Divider Value The value the K2-Divider operates is K2DIV+1. K1DIV [22:16] rw K1-Divider Value The value the K1-Divider operates is K1DIV+1.
Page 220 TC1784 System Control Unit (SCU) Field Bits Type Description VCOBYST VCO Bypass Status Freerunning / Normal Mode is entered Prescaler Mode is entered PWDSTAT PLL_ERAY Power-saving Mode Status PLL_ERAY Power-saving Mode was not entered PLL_ERAY Power-saving Mode was entered VCOLOCK...
Page 221 TC1784 System Control Unit (SCU) Field Bits Type Description K1RDY K1 Divider Ready Status This bit indicates if the K1-divider operates on the configured value or not. this is of interest if the values is changed. K1-Divider is not ready to operate with the new...
Page 222 TC1784 System Control Unit (SCU) Field Bits Type Description VCOPWD VCO Power Saving Mode Normal behavior The VCO is put into a Power Saving Mode and can no longer be used. SETFINDIS Set Status Bit PLLERAYSTAT.FINDIS Bit PLLERAYSTAT.FINDIS is left unchanged Bit PLLERAYSTAT.FINDIS is set.
Page 223 TC1784 System Control Unit (SCU) PLLERAYCON1 PLL_ERAY Configuration 1 Register (02C Reset Value: 000F 000F K1DIV K2DIV Field Bits Type Description K2DIV [6:0] K2-Divider Value The value the K2-Divider operates is K2DIV+1. K1DIV [22:16] rw K1-Divider Value The value the K1-Divider operates is K1DIV+1.
Page 224 TC1784 System Control Unit (SCU) Field Bits Type Function FPIDIV [3:0] FPI-Bus Divider Reload Value 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 LMBDIV [11:8] LMB-Bus Divider Reload Value 0000 0001 0010...
Page 225 TC1784 System Control Unit (SCU) Field Bits Type Function PCPDIV [27:24] rw PCP Divider Reload Value 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Lock Status This bit indicates if the register can be updated with a new value or if the register is locked and a write action from the bus side has no effect.
Page 226 TC1784 System Control Unit (SCU) CCUCON1 CCU Clock Control Register 1 (034 Reset Value: 8000 0B01 REFCLKDIV MCDSDIV Field Bits Type Function MCDSDIV [3:0] MCDS Divider Reload Value 0000 MCDS 0001 MCDS 0010 MCDS 0011 MCDS 0100 MCDS 0101 MCDS...
Page 227 TC1784 System Control Unit (SCU) Field Bits Type Function REFCLKDIV [11:8] Reference Clock for MCDS Divider Reload Value 0000 REFCLK1 0001 REFCLK1 0010 REFCLK1 0011 REFCLK1 0100 REFCLK1 0101 REFCLK1 0110 REFCLK1 0111 REFCLK1 1000 REFCLK1 1001 REFCLK1 1010 REFCLK1...
Page 228 TC1784 System Control Unit (SCU) EXTCON External Clock Control Register (03C Reset Value: 0000 0000 DIV1 SEL1 AINS SEL0 Field Bits Type Description External Clock Enable for EXTCLK0 No external clock is provided The configured external clock is provided SEL0...
Page 229 TC1784 System Control Unit (SCU) Field Bits Type Description GPTAINSEL GPTA Input Select This value defines if either the input from P2.8 or the configured output frequency for EXTCLK0 is used as input for IN0 of the GPTA module. P2.8 is selected as input for IN0 of the GPTA...
Page 230 TC1784 System Control Unit (SCU) Fractional Divider Register (038 Reset Value: 0000 0000 RESULT STEP Field Bits Type Description STEP [9:0] Step Value In Normal Divider Mode, STEP contains the reload value for RESULT. In Fractional Divider Mode, this bit field determines the 10-bit value that is added to RESULT with each input clock cycle.
Page 231 TC1784 System Control Unit (SCU) Field Bits Type Description DISCLK Disable Clock Clock generation of is enabled according to the setting of bit field DM. Fractional divider is stopped. No change except when writing bit field DM. This bit is cleared when external clock enable input is asserted.
Page 232: Module Clock Generation
TC1784 System Control Unit (SCU) 3.1.2 Module Clock Generation The TC1784 on-chip modules have two registers for clock control: • Clock Control Register CLC • Fractional Divider Register FDR The following sections describes the general functionality of CLC and FDR. The module- specific implementation details are described in the corresponding module chapters.
Page 233: Clock Control Register Clc
TC1784 System Control Unit (SCU) 3.1.2.1 Clock Control Register CLC All CLC registers have basically the same bit and bit field layout. However, not all CLC register functions are implemented for each peripheral module. Table 3-1 defines in detail which bits and bit fields of the CLC registers are implemented for each clock control register.
Page 234 When an application is suspended, normal operation of the application’s program is halted, and the TC1784 begins (or resumes) executing a special debug monitor program. If bit SPEN is set, the operation of the peripheral module is stopped when the Suspend Mode request is generated.
Page 235 SPEN bit. Module Clock Divider Control Peripheral modules of the TC1784 can have a RMC control bit field in their CLC registers. This Run Mode Clock control bit field makes it possible to slow down the CLC clock via a programmable clock divider circuit.
Page 236 Module Clock Register Implementations Table 3-1 shows which of the CLC register bits/bit fields are implemented for each peripheral module in the TC1784 and which modules are equipped with a fractional divider. Table 3-1 Clock Generation Implementation of the TC1784 Peripheral Modules...
Page 237 TC1784 System Control Unit (SCU) Fractional Divider Operation The fractional divider divides the input clock either by the factor 1/n or by a fraction of n/1024 for any value of n from 0 to 1023, and outputs the clock signal, .
Page 238 TC1784 System Control Unit (SCU) Fractional divider Mode When the Fractional Divider Mode is selected (MOD_FDR.DM = 10 ), the module clock is derived from the bus clock by division of a fraction of n/1024 for any value of n from 0 to 1023. In general, the Fractional Divider Mode makes it possible to program the average module clock frequency with a higher accuracy than in Normal Divider Mode.
Page 239 TC1784 System Control Unit (SCU) Table 3-2 Fractional Divider Function Table Mode Result Operation of Fractional Divider Normal Mode – unchanged inactive switched off continuously active Normal Divider updated Mode Fractional Divider Mode unchanged inactive switched off Suspend unchanged inactive...
Page 240 TC1784 System Control Unit (SCU) Table 3-3 FDR Register Implementations FDR Register Suspend Mode Acknowledge Operation ENHW CAN_FDR Acknowledge depends on module state – FADC_FDR Acknowledge depends on module state – GPTA0_FDR Always immediately acknowledged; from independently from module states...
Page 241 TC1784 System Control Unit (SCU) Module CLC Register MOD_CLC Clock Control Register Reset Value: Module-specific Field Bits Type Description DISR Module Disable Request Bit Used for enable/disable control of the module. Module disable is not requested Module disable is requested...
Page 242 TC1784 System Control Unit (SCU) Field Bits Type Description SBWE Module Suspend Bit Write Enable for OCDS Determines whether SPEN and FSOE are write- protected. Bits SPEN and FSOE are write-protected Bits SPEN and FSOE are overwritten by respective value of SPEN or FSOE Reading this bit returns always 0.
Page 243 TC1784 System Control Unit (SCU) Field Bits Type Description STEP [9:0] Step Value In Normal Divider Mode, STEP contains the reload value for RESULT. In Fractional Divider Mode, this bit field determines the 10-bit value that is added to RESULT with each input clock cycle.
Page 244 TC1784 System Control Unit (SCU) Field Bits Type Description RESULT [25:16] Result Value In Normal Divider Mode, RESULT acts as reload counter (addition +1). In Fractional Divider Mode, this bit field contains the result of the addition RESULT + STEP.
Page 245: Reset Operation
TC1784 System Control Unit (SCU) Reset Operation This section describes the conditions under which the TC1784 will be reset and the reset operation configuration and control. 3.2.1 Overview The following reset request triggers are available: • 1 External power-on hardware reset request trigger; PORST, (cold reset) •...
Page 246: Reset Sources Overview
Module Reset Behavior Table 3-5 lists how the various functions of the TC1784 are affected through a reset depending on the reset type. A “X” means that this block has at least some register/bits that are affected by this reset.
Page 247: General Reset Operation
TC1784 System Control Unit (SCU) Table 3-5 Effect of Reset on Device Functions (cont’d) Module / Function Application Debug Reset System Power-on Reset Reset Reset On-chip OVRAM Not affected, Not affected, Affected, Affected, Static reliable reliable un-reliable un-reliable RAMs LDRAM...
Page 248: Reset State Machine
TC1784 System Control Unit (SCU) 3.2.6 Reset State Machine There is one central Reset State Machine (RSM) controlling the reset generation for the complete device beside the JTAG reset domain. Note: The JTAG reset domain is controlled by the TRST pin.
Page 249 TC1784 System Control Unit (SCU) • Second to configure the reset length in a way that the reset outputs via the ESRx pins match with the reset input requirements of external blocks connected with the reset outputs. A reset counter RSTCNT is an 16-bit counter counting down from the reload value defined by RSTCNTCON.RELx (x = SA or D).
Page 250: De-Assertion Of A Reset
TC1784 System Control Unit (SCU) 3.2.8 De-assertion of a Reset The reset is de-asserted when all of the following conditions are fulfilled. • The reset counter has expired (reached zero) • No reset request trigger that is configured to generate the same reset is currently asserted 3.2.8.1...
Page 251: Specific Reset Triggers
TC1784 System Control Unit (SCU) 3.2.9.1 Specific Reset Triggers These triggers lead to a predefined reset if the trigger is asserted. Additionally these triggers can not be enabled / disabled. All specific reset are listed in Table 3-8. Table 3-8...
Page 252: Reset Controller Registers
TC1784 System Control Unit (SCU) 3.2.12 Reset Controller Registers 3.2.12.1 Status Registers After a reset has been executed, the Reset Status registers provide information on the source of the last reset(s). The reset status registers are updated upon each reset cycle.
Page 253 TC1784 System Control Unit (SCU) Field Bits Type Description ESR1 Reset Request Trigger Reset Status for ESR1 The last reset was not requested by this reset trigger The last reset was requested by this reset trigger Note: This bit is set if the ESR1 pin is configured as...
Page 254: Configuration Registers
TC1784 System Control Unit (SCU) Field Bits Type Description Reset Request Trigger Reset Status for Cerberus System Reset The last reset was not requested by this reset trigger The last reset was requested by this reset trigger Reset Request Trigger Reset Status for Cerberus...
Page 255 TC1784 System Control Unit (SCU) RSTCNTCON Reset Counter Control Register (054 Reset Value: 05BE 05BE RELD RELSA Field Bits Type Description RELSA [15:0] System Application Reset Counter Reload Value This bit field defines the reload value of RSTCNTA. This value is always used when counter RSTCNTA is started.
Page 256 TC1784 System Control Unit (SCU) Field Bits Type Description ESR0 [1:0] ESR0 Reset Request Trigger Reset Configuration This bit field defines which reset is generated by a reset request trigger from ESR0 reset. No reset is generated for a trigger of ESR0...
Page 257 TC1784 System Control Unit (SCU) Field Bits Type Description Reserved Should be written with 1. Reserved [31:10] Should be written with 0. ARSTDIS Application Reset Disable Register (05C Reset Value: 0000 0000 Field Bits Type Description STMDIS STM Disable Reset This bit field defines if an Application Reset leads to an reset for the STM.
Page 258 TC1784 System Control Unit (SCU) SWRSTCON Software Reset Configuration Register (060 Reset Value: 0000 0000 SWCFG Field Bits Type Description SWBOOT Software Boot Configuration Selection Bit field STSTAT.HWCFG is not updated with the content of SWCFG upon an Application Reset Bit field STSTAT.HWCFG is updated with the...
Page 259: External Interface
TC1784 System Control Unit (SCU) External Interface The SCU provides interface pads for system purpose. Various functions are covered by these pins. Due to the different tasks some of the pads can not be shared with other functions but most of them can. The following functions are covered by the SCU controlled pads: •...
Page 260: Esrx As Reset Output
TC1784 System Control Unit (SCU) In order to be safely recognized ESR0/ESR1 has to be active for a minimum of 2 clock cycles. The input signal ESR0/ESR1 have digital filters (3-stage median filters), that can be disabled. A 3-stage median filter samples with three consecutive clock cycles and the output is defined by the majority of the three sampled values.
Page 261: Esr Registers
TC1784 System Control Unit (SCU) 3.3.1.3 ESR Registers ESRCFG0 ESR0 Configuration Register (070 Reset Value: 0000 0110 ESRCFG1 ESR1 Configuration Register (074 Reset Value: 0000 0090 EDCON Field Bits Type Description DFEN Digital Filter Enable This bit defines if the 3-stage median filter of the ESR0 is used or bypassed.
Page 262 TC1784 System Control Unit (SCU) inputs, and push-pull or open-drain functionality for outputs can be selected by the corresponding bit fields PCx (x = 0-1). IOCR Input/Output Control Register (0A0 Reset Value: 0020 10E0 Field Bits Type Description [7:4] Control for ESR0 Pin...
Page 263 TC1784 System Control Unit (SCU) Pad Control Coding Table 3-9 describes the coding of the PC0 bit field that determine the port line functionality. Table 3-9 PC0 Coding PC0[3:0] Output Selected Pull-up/Pull-down/ Characteristics Selected Output Function 0X00 Input is active and No input pull device connected not inverted;...
Page 264 TC1784 System Control Unit (SCU) Pad Control Coding Table 3-10 describes the coding of the PC1 bit field that determine the port line functionality. Table 3-10 PC1 Coding PC1[3:0] Output Selected Pull-up/Pull-down/ Characteristics Selected Output Function 0X00 Input is active and No input pull device connected not inverted;...
Page 265 TC1784 System Control Unit (SCU) Output Register (0A4 Reset Value: 0000 0000 Field Bits Type Description Output Bit x (x = 0-1) This bit determines the level at the output pin ESRx if the output is selected as GPIO output.
Page 266 TC1784 System Control Unit (SCU) Output Modification Register (0A8 Reset Value: 0000 0000 Field Bits Type Description Set Bit x (x = 0-1) Setting this bit will set or toggle the corresponding bit in the output register OUT. The function of this bit is...
Page 267 TC1784 System Control Unit (SCU) Input Register The logic level of a GPIO pin can be read via the read-only port input register IN. Reading the IN register always returns the current logical value at the GPIO pin independently whether the pin is selected as input or output.
Page 268: External Request Unit (Eru)
The detected events can also be used by other modules to trigger or to gate module- specific actions. 3.3.2.1 Introduction The ERU of the TC1784 can be split in three main functional parts: • 4 independent Input Channels x for input selection and conditioning of trigger or gating functions •...
Page 269 TC1784 System Control Unit (SCU) events (event detected = event flag becomes set, independent of the polarity of the original input signals). • The Connecting Matrix distributes the events and status flags generated by the Input Channels to the Output Channels.
Page 270: External Request Select Unit (Ers)
TC1784 System Control Unit (SCU) 3.3.2.2 ERU Pin Connections Figure 3-21 shows the ERU input connections. ERS0 ERS1 P3.10 Input 00 P3.11 Input 10 P0.14 Input 01 P0.15 Input 11 GPTA0_TRIG01 Input 02 Not connected Input 12 MSC0_FCLP Input 03...
Page 271: Event Trigger Logic (Etl)
TC1784 System Control Unit (SCU) Input x0 Input x1 Input channel x Input x2 Input x3 EICRy.EXISx ERU_ERS_block Figure 3-22 External Request Select Unit Overview The ERS unit for channel x is controlled via bit field ERCIy.EXISx. 3.3.2.4 Event Trigger Logic (ETL) For each Input Channel x, an event trigger logic ETLx derives a trigger event and a status from the input channel x delivered by the associated ERSx unit.
Page 272 TC1784 System Control Unit (SCU) EICRm. EICRm. FMR. FMR. FENx LDENx clear Modify clear Status Flag EIFR.INTFx Status EIFR.INTFx to all OGU y Flag Input Detect channel x edge event ERSx Event TRx0 to (edge) OGU0 TRx1 to Enable Select...
Page 273: Connecting Matrix
TC1784 System Control Unit (SCU) 3.3.2.5 Connecting Matrix The connecting matrix distributes the trigger signals (TRxy) and status signals (EIFR.INPFx) from the different ETLx units between the OGUy units. Figure 3-24 provides a complete overview of the connections between the ETLx and the OGUz units.
Page 274 TC1784 System Control Unit (SCU) EIFR .INTF0 Pattern ERU_PDOUT0 Detection TR00 Inputs ERU_GOUT0 TR01 ERU_IOUT0 ETL0 OGU0 TR02 ERU_TOUT0 TR03 Trigger Inputs TRx0 EIFR .INTF1 Pattern ERU_PDOUT1 Detection TR10 Inputs ERU_GOUT1 TR11 ETL1 OGU1 ERU_IOUT1 TR12 ERU_TOUT1 TR13 Trigger Inputs TRx1 EIFR .INTF2...
Page 275: Output Gating Unit (Ogu)
TC1784 System Control Unit (SCU) 3.3.2.6 Output Gating Unit (OGU) Each OGUy unit combines the available trigger events and status flags from the Input Channels and distributes the results to the system. Figure 3-25 illustrates the logic blocks within an OGUy unit. All functions of an OGUy unit are controlled by the associated IGCRm registers, one for each pair of output channels e.g.
Page 276 TC1784 System Control Unit (SCU) • ERU_PDOUTy to directly output the pattern match information for gating purposes in other modules (pattern match = 1). • ERU_GOUTy to output the pattern match or pattern miss information (inverted pattern match), or a permanent 0 or 1 under software control for gating purposes in other modules.
Page 277: Eru Output Connections
TC1784 System Control Unit (SCU) events to support interrupt generation or to trigger other module functions (e.g. in an ADC). The event is indicated when the pattern detection result changes and PDRR.PDRy becomes updated. The interrupt generation in the OGUy is based on the trigger ERU_TOUTy that can be gated (masked) with the pattern detection result ERU_PDOUTy.
Page 278 TC1784 System Control Unit (SCU) Table 3-12 ERU Output Connections in TC1784 Output from/to I/O to Can be used to/as Module OGUy OGU0 Outputs ERU_ not connected pattern detection output PDOUT0 ERU_ not connected gated pattern detection output GOUT0 ERU_...
Page 279: External Request Unit Registers
TC1784 System Control Unit (SCU) Table 3-12 ERU Output Connections in TC1784 (cont’d) Output from/to I/O to Can be used to/as Module OGUy ERU_ Interrupt Generation interrupt output IOUT2 DMA channel 02 DMA channel 06 ADC trigger input FADC input FADC_TSC...
Page 280 TC1784 System Control Unit (SCU) EICR0 External Input Channel Register 0 (080 Reset Value: 0000 0000 INP1 EXIS1 INP0 EXIS0 Field Bits Type Description EXIS0 [5:4] External Input Selection 0 This bit field determines which input line is selected for Input Channel 0.
Page 281 TC1784 System Control Unit (SCU) Field Bits Type Description LDEN0 Level Detection Enable 0 This bit determines if bit INTF0 is cleared automatically if an edge of the input Input Channel 0 is detected, which has not been selected (rising edge with REN0 = 0 or falling edge with FEN0 = 0).
Page 282 TC1784 System Control Unit (SCU) Field Bits Type Description FEN1 Falling Edge Enable 1 This bit determines if the falling edge of Input Channel 1 is used to set bit INTF1. The falling edge is not used The detection of a falling edge of Input Channel...
Page 283 TC1784 System Control Unit (SCU) Field Bits Type Description INP1 [30:28] Input Node Pointer This bit field determines the destination (output channel) for trigger event 1 (if enabled by EIEN1). The event of input channel 1 triggers output channel 0 (signal INT10)
Page 284 TC1784 System Control Unit (SCU) Field Bits Type Description EXIS2 [5:4] External Input Selection 2 This bit field determines which input line is selected for Input Channel 2. Input 20 is selected Input 21 is selected Input 22 is selected...
Page 285 TC1784 System Control Unit (SCU) Field Bits Type Description INP2 [14:12] Input Node Pointer This bit field determines the destination (output channel) for trigger event 2 (if enabled by EIEN2). The event of input channel 2 triggers output channel 0 (signal INT20)
Page 286 TC1784 System Control Unit (SCU) Field Bits Type Description LDEN3 Level Detection Enable 3 This bit determines if bit INTF3 is cleared automatically if an edge of the input Input Channel 3 is detected, which has not been selected (rising edge with REN3 = 0 or falling edge with FEN3 = 0).
Page 287 TC1784 System Control Unit (SCU) EIFR External Input Flag Register (088 Reset Value: 0000 0000 Field Bits Type Description INTFx External Interrupt Flag of Channel x (x = 0-3) This bit monitors the status flag of the event trigger condition for the input channel x. This bit is...
Page 288 TC1784 System Control Unit (SCU) Field Bits Type Description Set Flag INTFx for Channel x (x = 0-3) Setting this bit will set the corresponding bit INTFx in register EIFR. Reading this bit always delivers a 0. The bit x in register EIFR is not modified...
Page 289 TC1784 System Control Unit (SCU) The Interrupt Gating Control Registers IGCR0 and IGCR1 contain bits to enable the pattern detection and to control the gating for output channel 0 to 3. IGCR0 Interrupt Gating Register 0 (094 Reset Value: 0000 0000...
Page 290 TC1784 System Control Unit (SCU) Field Bits Type Description IGP0 [15:14] Interrupt Gating Pattern 0 Bit field IGP0 determines how the pattern detection influences the output lines GOUT0 and IOUT0. The detected pattern is not taken into account. An activation of IOUT0 is always possible due to a trigger event.
Page 291 TC1784 System Control Unit (SCU) Field Bits Type Description IGP1 [31:30] Interrupt Gating Pattern 1 Bit field IGP1 determines how the pattern detection influences the output lines GOUT1 and IOUT1. The detected pattern is not taken into account. An activation of IOUT1 is always possible due to a trigger event.
Page 292 TC1784 System Control Unit (SCU) Field Bits Type Description IPEN2x Interrupt Pattern Enable for Channel 2 (x = 0-3) Bit IPEN2x determines if the flag INTFx of channel x takes part in the pattern detection for the gating of the requests for the output signals GOUTy and IOUTy.
Page 293 TC1784 System Control Unit (SCU) Field Bits Type Description IPEN3x 16+x Interrupt Pattern Enable for Channel 3 (x = 0-3) Bit IPEN3x determines if the flag INTFx of channel x takes part in the pattern detection for the gating of the requests for the output signals GOUTy and IOUTy.
Page 294: Power Management
TC1784 System Control Unit (SCU) Power Management This section describes the power management system of the TC1784. Topics covered here include the internal system interfaces, external interfaces, and the operations of the CPU and peripherals. 3.4.1 Power Management Overview The TC1784 power-management system allows software to configure the various processing units so that they automatically adjust to draw the minimum necessary power for the application.
Page 295: Power Management Modes
If any of these conditions arise, the TC1784 immediately awakens and returns to Run Mode. If it is awakened by a reset, the TC1784 system begins its reset sequence. If it is awakened by a Watchdog Timer overflow event, it executes the instruction following the one that was last executed before Idle Mode was entered.
Page 296: Sleep Mode
Sleep Mode will switch back to their selected Run Mode operation. 3.4.3 Power Management Control and Status Register, PMCSR The set of registers used for power management is divided between central TC1784 components and peripheral components. The PMCSR register provides software control User´s Manual 3-113 V1.1, 2011-05...
Page 297 Sleep Mode behavior of each peripheral component is programmable. When entering Idle Mode and Sleep Mode, the Power Management directly controls TC1784 components such as the CPU, but indirectly controls peripheral components through their clock control registers.
Page 298 TC1784 System Control Unit (SCU) Field Bits Type Function [7:2], Reserved [31:11] Read as 0; should be written with 0. User´s Manual 3-115 V1.1, 2011-05 32-bit SCU, V1.18...
Page 299: Software Boot Support
TC1784 System Control Unit (SCU) Software Boot Support In order to determine the correct starting point of operation for the software a minimum of hardware support is required. As much as possible is done via software. Some decisions have to be done in hardware because they must be known before any software is operational.
Page 300: Start-Up Registers
TC1784 System Control Unit (SCU) 3.5.3 Start-up Registers 3.5.3.1 Start-up Status Register Register STSTAT contains the information required by the boot software to identify the different start-up settings that can be selected. STSTAT Start-up Status Register (0C0 Reset Value: 0000 8000...
Page 301 TC1784 System Control Unit (SCU) Field Bits Type Description Mode Mode This bit indicates if the Test Mode is entered or not. A Test Mode can be selected Normal Mode is selected FCBAE Flash Config. Sector Access Enable Flash config sector is not accessible. Instead the flash memory area is accessed.
Page 302 TC1784 System Control Unit (SCU) STCON Start-up Configuration Register (0C4 Reset Value: 0000 8000 HWCFG Field Bits Type Description HWCFG [7:0] Hardware Configuration Setting Writing to this bit field updates bit field STSTAT.HWCFG. Reading this bit field returns zero. SFCBAE Set Flash Config.
Page 303: Ecc Error Handling
TC1784 System Control Unit (SCU) ECC Error Handling The on-chip RAM and flash modules check ECC information during read accesses and in case of an error a signal is generated. These signals are combined and trigger a trap. clear ECCCLR.
Page 304: Ecc Registers
TC1784 System Control Unit (SCU) 3.6.2 ECC Registers ECCCON ECC Control Register (0D0 Reset Value: 0000 FFFF Field Bits Type Description ECCENLDRA ECC Error Trap Enable for LDRAM and DCACHE Memory This bit determine whether a trap is requested if an uncorrected ECC error is detected in the LDRAM / DCACHE memory.
Page 305 TC1784 System Control Unit (SCU) Field Bits Type Description ECCENPTAG ECC Error Trap Enable for Program Cache TAG RAM Memory This bit determine whether a trap is requested if an uncorrected ECC error is detected in the program cache TAG RAM memory.
Page 306 TC1784 System Control Unit (SCU) Field Bits Type Description [31:16] Reserved Read as 0; should be written with 0. Note: Register ECCCON is Endinit-protected for write operations. ECCSTAT ECC Status Register (0D4 Reset Value: 0000 0000 Field Bits Type Description...
Page 307 TC1784 System Control Unit (SCU) Field Bits Type Description PTAG ECC Error Flag for Program Cache TAG RAM Memory This bit indicate whether an ECC error has been detected in the program TAG RAM memory. No ECC error detected ECC error is detected...
Page 308 TC1784 System Control Unit (SCU) ECCCLR ECC Clear Register (0D8 Reset Value: 0000 0000 Field Bits Type Description LDRAM Clear LDRAM and DCACHE EEC Error Status No action Setting this bit clears bit EECSTAT.LDRAM This bit always read as 0.
Page 309 TC1784 System Control Unit (SCU) Field Bits Type Description CMEM Clear Parameter Code Memory EEC Error Status No action Setting this bit clears bit EECSTAT.CMEM This bit always read as 0. Clear CAN Memory EEC Error Status No action Setting this bit clears bit EECSTAT.CAN This bit always read as 0.
Page 310: Die Temperature Measurement
TC1784 System Control Unit (SCU) Die Temperature Measurement The Die Temperature Sensor (DTS) generates a measurement result that indicates directly the current temperature. The result of the measurement is displayed via bit field DTSSTAT.RESULT. In order to start one measurement bit DTSCON.START needs to be set.
Page 311: Die Temperature Sensor Register
TC1784 System Control Unit (SCU) 3.7.1 Die Temperature Sensor Register DTSCON Die Temperature Sensor Control Register(0E4 Reset Value: 0000 0001 Field Bits Type Description Sensor Power Down This bit defines the DTS power state. The DTS is powered The DTS is not powered...
Page 312 TC1784 System Control Unit (SCU) DTSSTAT Die Temperature Sensor Status Register(0E0 Reset Value: 0000 0000 RESULT Field Bits Type Description RESULT [9:0] Result of the DTS Measurement This bit field shows the result of the DTS measurement. The value given is directly related to the die temperature.
Page 313: Watchdog Timer
The WDT provides a highly reliable and secure way to detect and recover from software or hardware failure. The WDT helps to abort an accidental malfunction of the TC1784 in a user-specified time period. When enabled, the WDT can cause the TC1784 system to be reset if the WDT is not serviced within a user-programmable time period.
Page 314: The Endinit Function
Hence, its function is explained first. There are a number of registers in the TC1784 that are usually programmed only once during the initialization sequence of the application. Modification of such registers during normal application run can have a severe impact on the overall operation of modules or the entire system.
Page 315 As a solution, WDT_CON0 (the register with the ENDINIT bit) should be read back once before Endinit-protected registers are accessed the first time after bit ENDINIT has been cleared. Table 3-15 TC1784 Registers Protected via the Endinit Feature Register Name Description mod_CLC...
Page 316: Password Access To Wdt_Con0
TC1784 System Control Unit (SCU) Table 3-15 TC1784 Registers Protected via the Endinit Feature (cont’d) Register Name Description SCU_ESRCFG0 All ESR control registers are protected SCU_ESRCFG1 SCU_EMSR The emergency stop register SCU_TRAPSET The trap set and disable register SCU_TRAPDIS SCU_ECCCON...
Page 317: Modify Access To Wdt_Con0
TC1784 System Control Unit (SCU) of WDT_CON0 or WDT_CON1, it is always required to modify the read value (at least bits 1 and [7:4]) to get the correct password. This prevents a malfunction from accidentally reading a WDT register’s contents and writing it to WDT_CON0 as an unlocking password.
Page 318: Access To Endinit-Protected Registers
TC1784 System Control Unit (SCU) 3.8.3.3 Access to Endinit-Protected Registers If some or all of the system’s Endinit-protected registers must be changed during run time of an application, access can be re-opened. To do this, WDT_CON0 must first be unlocked with a Valid Password Access. In the subsequent Valid Modify Access, ENDINIT can be cleared.
Page 319 TC1784 System Control Unit (SCU) • Normal Mode • Disable Mode • Prewarning Mode The following overview describes these modes and how the WDT changes from one mode to the other. Time-Out Mode The Time-Out Mode is entered after an Application Reset or when a valid Password...
Page 320: Wdt Reset Behavior
If the Watchdog induced reset occurs twice, a severe system malfunction is assumed and the TC1784 is held in reset until a System Reset occurs. This prevents the device from being periodically reset if, for instance, connection to the external memory has been lost such that even system initialization could not be performed.
Page 321: Wdt Operation During Power-Saving Modes
TC1784 System Control Unit (SCU) permanent request is generated. This internal flag is cleared by any System Reset or when bit WDT_CON1.CLRIRF is set AND bit WDT_CON0.ENDINIT is set too. Please note that a correct service of the WDT does not clear this internal flag. Bit WDT_CON1.CLRIRF can only be set when bit WDT_CON0.ENDINIT is cleared.
Page 322: Suspend Mode Support
TC1784 System Control Unit (SCU) (WDT_SR.TIM) from 7FFF to 8000 , the CPU is awakened and continues to execute the instruction following the instruction that was last executed before entering the Idle or Sleep Mode. Note: Before switching into a non-running power-management mode, software should perform a Watchdog service sequence.
Page 323 TC1784 System Control Unit (SCU) WDT_CON0 WDT Control Register 0 (F000 05F0 Reset Value: FFFC 0002 HPW1 HPW0 INIT Field Bits Type Description ENDINIT End-of-Initialization Control Bit Access to Endinit-protected registers is permitted (default after Application Reset) Access to Endinit-protected registers is not...
Page 324 TC1784 System Control Unit (SCU) Field Bits Type Description HPW0 [3:2] Hardware Password 0 This bit field must be written with the value of the bits WDT_CON1.DR and WDT_CON1.IR during a Password Access. This bit field must be written with 0s during a Modify Access to WDT_CON0.
Page 325 TC1784 System Control Unit (SCU) WDT_CON1 WDT Control Register 1 (F000 05F4 Reset Value: 0000 0000 Field Bits Type Description CLRIRF Clear Internal Reset Flag This bit is used to request a clear of the internal flag storing the information about the first WDT reset request.
Page 326: Watchdog Timer Status Register
TC1784 System Control Unit (SCU) Field Bits Type Description Disable Request Control Bit Request to enable the WDT Request to disable the WDT This bit can only be modified if WDT_CON0.ENDINIT is cleared. WDT_SR.DS is updated when ENDINIT is set again. As long as ENDINIT is cleared, bit WDT_SR.DS controls the current enable/disable...
Page 327 TC1784 System Control Unit (SCU) Field Bits Type Description Watchdog Access Error Status Flag No Watchdog access error A Watchdog access error has occurred This bit is set when an illegal Password Access or Modify Access to register WDT_CON0 was attempted.
Page 328 TC1784 System Control Unit (SCU) Field Bits Type Description Watchdog Time-Out Mode Flag The Watchdog is not operating in Time-Out Mode The Watchdog is operating in Time-Out Mode (default after Application Reset) This bit is set when Time-Out Mode is entered. It is automatically cleared when Time-Out Mode is left.
Page 329: Emergency Stop Output Control
System Control Unit (SCU) Emergency Stop Output Control The emergency stop feature of the TC1784 allows for a fast emergency reaction on an external event without the intervention of software. In an emergency case, the outputs can be selectively put immediately to a well-defined logic state (for more information see the port chapter).
Page 330 TC1784 System Control Unit (SCU) In Asynchronous Mode (selected by EMSR.MODE = 1), the occurrence of an active level at the port input immediately activates the emergency stop signal. Of course, a valid-to-invalid transition of the port input (emergency case is released) also immediately deactivates the emergency stop signal.
Page 331: Emergency Stop Register
TC1784 System Control Unit (SCU) 3.9.1 Emergency Stop Register The Emergency Stop Register EMSR contains control and status bits/flags of the emergency stop input logic. EMSR Emergency Stop Register (100 Reset Value: 0000 0000 EMSFM Field Bits Type Description Input Polarity This bit determines the polarity of the input line.
Page 332 TC1784 System Control Unit (SCU) Field Bits Type Description EMSF Emergency Stop Flag This bit indicates if an emergency stop condition has occurred. An emergency stop has not occurred An emergency stop has occurred and signal emergency stop becomes active (if MODE = 0)
Page 333: Interrupt Generation
TC1784 System Control Unit (SCU) 3.10 Interrupt Generation The interrupt structure is shown in Figure 3-28. The interrupt request or the corresponding interrupt set bit (in register INTSET) can trigger the interrupt generation at the selected interrupt node x. The service request pulse is generated independently from the interrupt flag in register INTSTAT.
Page 334: Interrupt Control Registers
TC1784 System Control Unit (SCU) 3.10.1 Interrupt Control Registers INTSTAT Interrupt Status Register (110 Reset Value: 0000 0000 ERUI ERUI ERUI ERUI DTSI FL0I Field Bits Type Description WDTI Watchdog Timer Interrupt Request Flag This bit is set if the WDT Prewarning Mode is entered and bit is INTDIS.WDTI = 0.
Page 335 TC1784 System Control Unit (SCU) Field Bits Type Description ERUI1 ERU Channel 1 Interrupt Request Flag This bit is set if the ERU channel 1 is active and bit is INTDIS.ERUI1 = 0. No interrupt was requested since this bit was...
Page 336 TC1784 System Control Unit (SCU) Field Bits Type Description DTSI DTS Interrupt Request Flag This bit is set if the DTS busy indication changes from to 0 and bit is INTDIS.DTSI = 0. No interrupt was requested since this bit was...
Page 337 TC1784 System Control Unit (SCU) Field Bits Type Description ERUI0 Set Interrupt Request Flag ERUI0 Setting this bit set bit INTSTAT.ERUI0. Clearing this bit has no effect. Reading this bit returns always zero. ERUI1 Set Interrupt Request Flag ERUI1 Setting this bit set bit INTSTAT.ERUI1.
Page 338 TC1784 System Control Unit (SCU) INTCLR Interrupt Clear Register (118 Reset Value: 0000 0000 ERUI ERUI ERUI ERUI DTSI FL0I Field Bits Type Description WDTI Clear Interrupt Request Flag WDTI Setting this bit clears bit INTSTAT.WDTI. Clearing this bit has no effect.
Page 339 TC1784 System Control Unit (SCU) Field Bits Type Description DTSI Clear Interrupt Request Flag DTSI Setting this bit clears bit INTSTAT.DTSI. Clearing this bit has no effect. Reading this bit returns always zero. Reserved [15:8] Read as 0; have to be written with 1.
Page 340 TC1784 System Control Unit (SCU) Field Bits Type Description ERUI1 Disable Interrupt Request ERU1 An interrupt request can be generated for this source No interrupt request can be generated for this source ERUI2 Disable Interrupt Request ERU2 An interrupt request can be generated for this...
Page 341 TC1784 System Control Unit (SCU) INTNP Interrupt Node Pointer Register (120 Reset Value: 0000 0000 ERU3 ERU2 ERU1 ERU0 Field Bits Type Description [1:0] Interrupt Node Pointer for Interrupt WDT This bit field defines the interrupt node, that is requested due to the set condition for bit INTSTAT.WDTI (if enabled by bit INTDIS.WDTI).
Page 342 TC1784 System Control Unit (SCU) Field Bits Type Description ERU2 [7:6] Interrupt Node Pointer for Interrupt ERU2 This bit field defines the interrupt node, that is requested due to the set condition for bit INTSTAT.ERUI2 (if enabled by bit INTDIS.ERUI2).
Page 343 TC1784 System Control Unit (SCU) SRC0 Service Request Control 0 Register (1FC Reset Value: 0000 0000 SRC1 Service Request Control 1 Register (1F8 Reset Value: 0000 0000 SRC2 Service Request Control 2 Register (1F4 Reset Value: 0000 0000 SRC3 Service Request Control 3 Register...
Page 344 TC1784 System Control Unit (SCU) Field Bits Type Description SETR Request Set Bit SETR is required to set SRR. No action Set SRR; bit value is not stored; read always returns 0; no action if CLRR is set also. [9:8], 11,...
Page 345: Nmi Trap Generation
TC1784 System Control Unit (SCU) 3.11 NMI Trap Generation The NMI trap structure is shown in Figure 3-29. The trap request trigger or the corresponding trap set bit (in register TRAPSET) can trigger the NMI trap generation. The trap flag can be cleared by software by writing to the corresponding bit in register TRAPCLR.
Page 346: Trap Control Registers
TC1784 System Control Unit (SCU) 3.11.1 Trap Control Registers TRAPSTAT Trap Status Register (124 Reset Value: 0000 0000 Field Bits Type Description ESR0T ESR0 Trap Request Flag This bit is set if an ESR0 event is triggered and bit is TRAPDIS.ESR0T is cleared.
Page 347 TC1784 System Control Unit (SCU) Field Bits Type Description WDTT WDT Trap Request Flag This bit is set if a WDT trap is indicated and bit is TRAPDIS.WDTT is cleared. No trap was requested since this bit was cleared the last time...
Page 348 TC1784 System Control Unit (SCU) Field Bits Type Description OSCHWDTT OSCWDT High Trap Request Flag This bit is set if a oscillator WDT of the PLL detects a high event and bit is TRAPDIS.OSCHWDTT cleared. No trap was requested since this bit was...
Page 349 TC1784 System Control Unit (SCU) Field Bits Type Description ERAYVCOLC ERAYVCOWDT Trap Request Flag This bit is set if a PLL_ERAY VCO Loss-of Oscillator Lock event is triggered and bit is TRAPDIS.ERAYXVCOLCKT cleared. No trap was requested since this bit was...
Page 350 TC1784 System Control Unit (SCU) Field Bits Type Description ESR0T Set Trap Request Flag ESR0T Setting this bit set bit TRAPSTAT.ESR0T. Clearing this bit has no effect. Reading this bit returns always zero. ESR1T Set Trap Request Flag ESR1T Setting this bit set bit TRAPSTAT.ESR1T.
Page 351 TC1784 System Control Unit (SCU) Field Bits Type Description Reserved [15:10] Read as 0; have to be written with 0. [31:16] r Reserved Read as 0; should be written with 0. TRAPCLR Trap Clear Register (12C Reset Value: 0000 0000...
Page 352 TC1784 System Control Unit (SCU) Field Bits Type Description OSCLWDTT Clear Trap Request Flag OSCLWDTT Setting this bit clears bit TRAPSTAT.OSCLWDTT. Clearing this bit has no effect. Reading this bit returns always zero. OSCHWDTT Clear Trap Request Flag OSCHWDTT Setting this bit clears bit TRAPSTAT.OSCHWDTT.
Page 353 TC1784 System Control Unit (SCU) TRAPDIS Trap Disable Register (130 Reset Value: 0000 FFFF Field Bits Type Description ESR0T Disable Trap Request ESR0T A trap request can be generated for this source No trap request can be generated for this...
Page 354 TC1784 System Control Unit (SCU) Field Bits Type Description OSCHWDTT Disable Trap Request OSCHWDTT A trap request can be generated for this source No trap request can be generated for this source OSCSPWDTT 7 Disable Trap Request OSCSPWDTT A trap request can be generated for this source...
Page 355: Miscellaneous System Control Register
3.12.1 GPTA Input IN1 Control In the TC1784, the input line IN1 of the GPTA module can be used to measure the baud rate of an ASC0 or ASC1 receiver input signal with GPTA. This feature is controlled by SYSCON.GPTAIS.
Page 356 TC1784 System Control Unit (SCU) SYSCON System Control Register (040 Reset Value: 0000 0000 GPTAIS Field Bits Type Description GPTAIS [3:2] GPTA Input Select This bit field selects the input that is used for IN1 of the GPTA module. For more information see either Section 3.12.1...
Page 357: Identification Registers
Type Description CHREV [7:0] Chip Revision Number This bit field indicates the revision number of the TC1784 device. The value of this bit field is defined in the TC1784 Data Sheet. CHID [15:8] Chip Identification Number This bit field defines the product by a unique number.
Page 358 Type Description CHREV [7:0] Chip Revision Number This bit field indicates the revision number of the TC1784 device. The value of this bit field is defined in the TC1784 Data Sheet. CHID [15:8] Chip Identification Number This bit field defines the product by a unique number.
Page 359 Type Description CHREV [7:0] Chip Revision Number This bit field indicates the revision number of the TC1784 device. The value of this bit field is defined in the TC1784 Data Sheet. CHID [15:8] Chip Identification Number This bit field defines the product by a unique number.
Page 360 MODREV Field Bits Type Description MODREV [7:0] Module Revision Number This bit field indicates the revision number of the TC1784 module (01 = first revision). MODTYPE [15:8] Module Type This bit field is C0 . It defines a 32-bit module...
Page 361 Bits Type Description DEPT [4:0] Department Identification Number = 00 : indicates the Automotive & Industrial microcontroller department within Infineon Technologies. MANUF [15:5] Manufacturer Identification Number This is a JEDEC normalized manufacturer code. MANUF = C1 stands for Infineon Technologies.
Page 362: Scu Kernel Registers
This section describes the kernel registers of the 32-bit SCU module. Most of 32-bit SCU kernel register names described in this section will be referenced in other parts of the TC1784 User´s Manual by the module name prefix “SCU_”. SCU Kernel Register Overview...
Page 363 TC1784 System Control Unit (SCU) Table 3-20 Register Overview of SCU Short Long Name Offset Access Mode Reset Description Name Addr. Read Write PLLERAY PLL_ERAY Status U, SV System Page 3-36 STAT Register Reset PLLERAY PLL_ERAY U, SV SV, E...
Page 364 TC1784 System Control Unit (SCU) Table 3-20 Register Overview of SCU Short Long Name Offset Access Mode Reset Description Name Addr. Read Write ESRCFG0 ESR0 U, SV SV, E System Page 3-78 Configuration Reset Register ESRCFG1 ESR1 U, SV SV, E...
Page 365 TC1784 System Control Unit (SCU) Table 3-20 Register Overview of SCU Short Long Name Offset Access Mode Reset Description Name Addr. Read Write PMCSR Power U, SV U, SV Application Page 3-114 Management Reset Control and Status Register – Reserved –...
Page 366 TC1784 System Control Unit (SCU) Table 3-20 Register Overview of SCU Short Long Name Offset Access Mode Reset Description Name Addr. Read Write EMSR Emergency Stop U, SV SV, E Application Page 3-148 Register Reset – Reserved – – INTSTAT...
Page 367 TC1784 System Control Unit (SCU) Table 3-20 Register Overview of SCU Short Long Name Offset Access Mode Reset Description Name Addr. Read Write SRC3 Service Request U, SV Application Page 3-160 Control Register 3 Reset SRC2 Service Request U, SV...
Page 368: Scu Address Area
TC1784 System Control Unit (SCU) 3.12.5 SCU Address Area Table 3-21 Registers Address Space - SCU Kernel Registers Module Base Address End Address Note F000 0500 F000 06FF User´s Manual 3-185 V1.1, 2011-05 32-bit SCU, V1.18...
Page 369: On-Chip System Buses And Bus Bridges
TC1784 On-Chip System Buses and Bus Bridges On-Chip System Buses and Bus Bridges The TC1784 has two independent on-chip buses: • Local Memory Bus (LMB) • System Peripheral Bus (SPB) Floating Point Unit TriCore 124 KB LDRAM 24 KB SPRAM...
Page 370: What Is New
Major differences of the AudoFuture On Chip Bus System architecture compared to AudoNG: • The TC1784 is based on two on chip busses (LMB, SPB). The remote peripheral bus (RPB) was removed. • The DMA is additionally connected to the LMB bus with a master interface.
Page 371: Local Memory Bus
TC1784 On-Chip System Buses and Bus Bridges Local Memory Bus The following terminology is used for the bus: Table 4-1 LMB Bus Terms Term Description Agent An LMB agent is any master or slave device which is connected to the LMB Bus.
Page 372: Block Transfers
TC1784 On-Chip System Buses and Bus Bridges 4.2.2.2 Block Transfers Block transfers are only issued in the following ways: 1. By the PMI and DMI in case of a cache miss. 2. By the PCP if it uses a BCOPY instruction.
Page 373: Lmb Basic Operation
TC1784 On-Chip System Buses and Bus Bridges 4.2.5 LMB Basic Operation Figure 4-2 describes some basic bus operations of the LMB. Bus Cycle Request/ Address Data Transfer 1 Grant Cycle Cycle Request/ Address Data Transfer 2 Grant Cycle Cycle Address...
Page 374: Local Memory Bus Controller Unit
TC1784 On-Chip System Buses and Bus Bridges Local Memory Bus Controller Unit The LMB in the TC1784 has an LMB Bus Control Unit (LBCU). 4.3.1 Basic Operation The LBCU handles the cycle sequences of the transfers which have been requested by the LMB master devices.
Page 375: Lmb Bus Default Master
TC1784 On-Chip System Buses and Bus Bridges 4.3.2.1 LMB Bus Default Master When no LMB master is requesting the LMB, it is granted to the LMB default master. This means, if the default master needs the LMB in the next cycle, it can enter the address cycle without running through a request/grant cycle.
Page 376: Lmb Bus Control Unit Registers
TC1784 On-Chip System Buses and Bus Bridges 4.3.4 LMB Bus Control Unit Registers Figure 4-4 Table 4-4 are showing the address maps with all registers of LMB Bus Control Unit (LBCU) module. LBCU Unit Register Overview Identification Control Registers Address/Data...
Page 377 TC1784 On-Chip System Buses and Bus Bridges Table 4-4 Registers Overview - LBCU Module Control Registers Short Description Offset Access Mode Reset Description Name Addr. Class Read Write LBCU_LE LBCU LMB Error Data Page 4-14 DATL Low Register LBCU_LE LBCU LMB Error Data...
Page 378: Lmb Bus Control Unit Control Registers
TC1784 On-Chip System Buses and Bus Bridges 4.3.4.1 LMB Bus Control Unit Control Registers The identification register allows the programmer version-tracking of the module. The table below shows the identification register which is implemented in the LBCU module. LBCU_ID Module Identification Register...
Page 379 TC1784 On-Chip System Buses and Bus Bridges LBCU_LEATT LBCU LMB Error Attribute Register (020 Reset Value: XXXX XXX0 WR SVM LOC NOS FPITAG Field Bits Type Description Lock Error Capture This bit indicates and controls whether the error- capture mechanism is unlocked or locked.
Page 380 TC1784 On-Chip System Buses and Bus Bridges Field Bits Type Description LMB Bus Lock State This bit indicates the bus lock state in case of an LMB bus error. LMB bus error occurred at an atomic transfer. LMB bus error occurred at a single or block transfer.
Page 381 TC1784 On-Chip System Buses and Bus Bridges Field Bits Type Description [31:28] LMB Bus Error Transaction Type This bit field indicates the type of transfer at which the LMB bus error occurred. 0000 8-bit data single transfer 0001 16-bit data single transfer...
Page 382 TC1784 On-Chip System Buses and Bus Bridges Field Bits Type Description LEADDR [31:0] LMB Bus Address This bit field holds the LMB address that has been captured at an LMB error. LEADDR only contains valid read data when bit LEC in the corresponding register LEATT is set.
Page 383 TC1784 On-Chip System Buses and Bus Bridges Field Bits Type Description LEDAT[63:32] [31:0] LMB Bus Address Bits [31:0] This bit field holds the upper 32-bit part of the 64-bit LMB data that has been captured at an LMB bus error.
Page 384: Local Memory Bus To Fpi Bus Interface (Lfi Bridge)
TC1784 On-Chip System Buses and Bus Bridges Local Memory Bus to FPI Bus Interface (LFI Bridge) This section describes the basic functionality of the LFI Bridge. 4.4.1 Functional Overview The LFI Bridge is a bi-directional bus bridge between the LMB and the System Peripheral FPI Bus (SPB).
Page 385 TC1784 On-Chip System Buses and Bus Bridges Note that this behavior occurs only at write operations via the LFI Bridge. It can also be triggered by an erroneous write cycle of a read-modify-write bus transaction. User´s Manual 4-17 V1.1, 2011-05...
Page 386: Lmb To Fpi Bridge Control Registers
TC1784 On-Chip System Buses and Bus Bridges 4.4.2 LMB to FPI Bridge Control Registers Table 4-7 Table 4-8 are showing the address maps with all registers of the LMB to FPI Bridge (LFI) module. LFI Register Identification Register LFI_ID LFI_CON...
Page 387: Lfi Register Description
TC1784 On-Chip System Buses and Bus Bridges 2) Read as 0. Should not be written. If it is written, it must be written with 0. 4.4.2.1 LFI Register Description The identification register allows the programmer version-tracking of the module. The table below shows the identification register which is implemented in the LFI module.
Page 388 Returns 0 if read; must be written with 0. LTAG [6:4] LMB Bus Tag ID In the TC1784, the bit field LTAG = 000 FTAG [11:8] FPI Bus (SPB) Tag ID In the TC1784, the bit field FTAG = 1011 , which reflects the tag number of the LFI Bridge on the SPB.
Page 389: System Peripheral Bus
• Support of atomic operations LDMST, ST.T and SWAP.W The functional units of the TC1784 are connected to the FPI Bus via FPI Bus interfaces. An FPI Bus interfaces acts as bus agents, requesting bus transactions on behalf of their functional unit, or responding to bus transaction requests.
Page 390 Some functional units operate only as slaves, while others can operate as either masters or slaves on the FPI Bus. In the TC1784, DMI and PMI (via the LFI Bridge), PCP and DMA (including Cerberus and MLI´s) operate as FPI Bus masters. On-chip peripheral units are typically FPI Bus slaves.
Page 391: Bus Transaction Types
2 word, 4 word, or 8 word transfers. Note: In general, block transfers (2 word, 4 word, or 8 word) cannot be executed in the TC1784 with peripheral units that operate as FPI Bus slaves during an FPI Bus transaction.
Page 392: Address Alignment Rules
TC1784 On-Chip System Buses and Bus Bridges 4.5.4 Address Alignment Rules FPI Bus address generation is compliant with the following rules: • Half-word transactions must have a half-word aligned address (A0 = 0). Half-word accesses on byte lanes 1 and 2 addresses are illegal.
Page 393 TC1784 On-Chip System Buses and Bus Bridges Bus Cycle Request/ Address Data Data Data Data Transfer 1 Grant Cycle Cycle Cycle Cycle Cycle Request/ Data Transfer 2 Address Cycle Grant Cycle MCA06110 Figure 4-7 FPI Bus Block Transactions User´s Manual 4-25 V1.1, 2011-05...
Page 394: Fpi Bus Control Unit (Sbcu)
BCU itself will drive the FPI Bus to prevent it from floating electrically. 4.6.1.1 Arbitration on the System Peripheral Bus The TC1784 SPB has three bus agents that can become a SPB bus master (DMA, LFI, PCP). Each agent is supplied an arbitration priority as shown in Table 4-9. DMA controller agent can be assigned to low, medium or high priority by software (via DMA Channel and OCDS control registers).
Page 395 TC1784 On-Chip System Buses and Bus Bridges If there is no request from an SPB bus master, the SPB is granted to a default master (LFI Bridge or PCP) which has been at last the active master. User´s Manual 4-27 V1.1, 2011-05...
Page 396: Starvation Prevention
TC1784 On-Chip System Buses and Bus Bridges 4.6.1.2 Starvation Prevention Starvation prevention is a feature of the SBCU that can take care that even requesting low priority master agents will be granted after a period, where the period length can be controlled by SBCU control registers.
Page 397 Code (ACK) Description NSC: No Special Condition. SPT: Split Transaction (not used in the TC1784). RTY: Retry. Slave can currently not respond to the access. Master needs to repeat the access later. ERR: Bus Error, last data cycle is aborted.
Page 398 TC1784 On-Chip System Buses and Bus Bridges Table 4-11 FPI Bus Operation Codes (OPC) Description 0000 Single Byte Transfer (8-bit) 0001 Single Half-Word Transfer (16-bit) 0010 Single Word Transfer (32-bit) 0100 2-Word Block Transfer 0101 4-Word Block Transfer 0110 8-Word Block Transfer...
Page 399: Bcu Debug Support
TC1784 On-Chip System Buses and Bus Bridges 4.6.3 BCU Debug Support For debugging purposes, the BCU has the capability for breakpoint generation support. This OCDS debug capability is controlled by the Cerberus module and must be enabled by it (indicated by bit SBCU_DBCNTL.EO).
Page 400: Signal Status Triggers
TC1784 On-Chip System Buses and Bus Bridges 4.6.3.2 Signal Status Triggers The signal status debug trigger event conditions are defined by the contents of the SBCU_DBBOS and SBCU_DBCNTL registers. Depending on the selected configuration a wide range of possibilities arise for the creation of a debug trigger event based on FPI Bus status signals.
Page 401: Grant Triggers
TC1784 On-Chip System Buses and Bus Bridges 4.6.3.3 Grant Triggers The signal status debug trigger event conditions are defined via the registers SBCU_DBGRNT and SBCU_DBCNTL. Depending on the configuration of these registers, any combination of FPI Bus master trigger events can be configured. Only the enabled masters in the SBCU_DBGRNT register are of interest for the grant debug trigger event condition.
Page 402: Combination Of Triggers
TC1784 On-Chip System Buses and Bus Bridges 4.6.3.4 Combination of Triggers The combination of the four debug trigger signals to the single BCU breakpoint trigger event is defined via the bits CONCOM[2:0] of register SBCU_DBCNTL (see Figure 4-11). The two address triggers are combined to one address trigger that is further combined with signal status and grant trigger signals.
Page 403 TC1784 On-Chip System Buses and Bus Bridges c) ONA1 = 01 means that the equal match condition for debug address 1 register is selected. d) ONG = 1 means that the grant debug trigger is enabled. e) CONCOM[2:0] = 101...
Page 404 TC1784 On-Chip System Buses and Bus Bridges OCDS Debug Example 3 • Task: Generation of a BCU debug trigger event on any access into address area 01FFFFFF to FFFFFFFF by the PCP. For this task the following programming settings for the BCU breakpoint logic must be executed: 1.
Page 405: System Bus Control Unit Registers
TC1784 On-Chip System Buses and Bus Bridges 4.6.4 System Bus Control Unit Registers Figure 4-12 Table 4-13 are showing the address maps with all registers of the System Bus Control Unit (SBCU) module. SBCU Control Registers Overview Control Registers Address/Data...
Page 406 TC1784 On-Chip System Buses and Bus Bridges Table 4-13 Registers Overview - SBCU Control Registers Short Description Offset Access Mode Reset Description Name Addr. Class Read Write SBCU_ SBCU Error Control U, SV SV Page 4-41 ECON Capture Register SBCU_...
Page 407: Sbcu Id Register Description
TC1784 On-Chip System Buses and Bus Bridges 4.6.4.1 SBCU ID Register Description The identification register allows the programmer version-tracking of the module. The table below shows the identification register which is implemented in the SBCU module. SBCU_ID Module Identification Register...
Page 408: Sbcu Control Registers Descriptions
TC1784 On-Chip System Buses and Bus Bridges 4.6.4.2 SBCU Control Registers Descriptions The SBCU Control Register controls the overall operation of the SBCU, including setting the starvation sample period, the bus time-out period, enabling starvation-protection mode, and error handling. SBCU_CON...
Page 409: Sbcu Error Registers Descriptions
TC1784 On-Chip System Buses and Bus Bridges 4.6.4.3 SBCU Error Registers Descriptions The capture of bus error conditions is enabled by setting SBCU_CON.DBG to 1. In case of a bus error, information about the condition will then be stored in the SBCU error capture registers.
Page 410 TC1784 On-Chip System Buses and Bus Bridges Field Bits Type Description ERRCNT [15:0] FPI Bus Error Counter ERRCNT is incremented on every occurrence of an FPI Bus error. ERRCNT is reset to 0000 after the SBCU_ECON register is read. TOUT...
Page 411 The FPI Bus operation codes are defined in Table 4-11. 1) In the TC1784, aborted accesses to a 0 wait state SPB slave may also increment ERRCNT when the slave generates an error acknowledge. Table 4-14 FPI Bus Read/Write Error Indication...
Page 412 TC1784 On-Chip System Buses and Bus Bridges SBCU_EDAT SBCU Error Data Capture Register (028 Reset Value: 0000 0000 FPIDAT Field Bits Type Description FPIDAT [31:0] Captured FPI Bus Address This bit field holds the 32-bit FPI Bus data that has been captured at an FPI Bus error.
Page 413: Sbcu Ocds Registers Descriptions
TC1784 On-Chip System Buses and Bus Bridges 4.6.4.4 SBCU OCDS Registers Descriptions SBCU_DBCNTL SBCU Debug Control Register (030 Reset Value: 0000 7003 ONA2 ONA1 Field Bits Type Description Status of SBCU Debug Support Enable This bit is controlled by the Cerberus and enables the SBCU debug support.
Page 414 TC1784 On-Chip System Buses and Bus Bridges Field Bits Type Description CONCOM0 Grant and Address Trigger Relation The grant phase trigger condition and the address trigger condition (see CONCOM1) are combined with a logical OR for further control The grant phase trigger condition and the...
Page 415 TC1784 On-Chip System Buses and Bus Bridges Field Bits Type Description ONA2 [25:24] Address 2 Trigger Control No address 2 trigger is generated An address 2 trigger event is generated if the FPI Bus address is equal to SBCU_DBADR2 An address 2 trigger event is generated if...
Page 416 TC1784 On-Chip System Buses and Bus Bridges Field Bits Type Description [3:2], Reserved [11:5], Read as 0; should be written with 0. [19:17], [23:22], [27:26] SBCU_DBGRNT SBCU Debug Grant Mask Register (034 Reset Value: 0000 FFFF Field Bits Type Description...
Page 417 TC1784 On-Chip System Buses and Bus Bridges Field Bits Type Description DMAM DMA Grant Trigger Enable, Medium Priority FPI Bus transactions with medium-priority DMA channels as bus master are enabled for grant trigger event generation FPI Bus transactions with medium-priority DMA...
Page 418 TC1784 On-Chip System Buses and Bus Bridges Field Bits Type Description ADR1 [31:0] Debug Trigger Address 1 This register contains the address for the address 1 trigger event generation. SBCU_DBADR2 SBCU Debug Address 2 Register (03C Reset Value: 0000 0000...
Page 419 TC1784 On-Chip System Buses and Bus Bridges Field Bits Type Description [3:0] Opcode for Signal Status Debug Trigger This bit field determines the type (opcode) of an FPI Bus transaction for which a signal status debug trigger event is generated (if enabled by DBCNTL.ONBOS0 = 1).
Page 420 TC1784 On-Chip System Buses and Bus Bridges Field Bits Type Description [7:5], Reserved [11:9], Read as 0; should be written with 0. [31:13] SBCU_DBGNTT SBCU Debug Trapped Master Register (044 Reset Value: 0000 FFFF Field Bits Type Description DMAH High-Priority DMA FPI Bus Master Status...
Page 421 TC1784 On-Chip System Buses and Bus Bridges Field Bits Type Description DMAM High-Priority DMA FPI Bus Master Status This bit indicates whether the DMA with a medium priority request was FPI Bus master when the break trigger event occurred. The medium-priority DMA was not the FPI bus master.
Page 422 TC1784 On-Chip System Buses and Bus Bridges SBCU_DBADRT SBCU Debug Trapped Address Register (048 Reset Value: 0000 0000 FPIADR Field Bits Type Description FPIADR [31:0] FPI Bus Address Status This register contains the FPI Bus address that was captured when the OCDS break trigger event occurred.
Page 423 TC1784 On-Chip System Buses and Bus Bridges Field Bits Type Description FPIOPC [3:0] FPI Bus Opcode Status This bit field indicates the type (opcode) of the FPI Bus transaction captured from the FPI Bus signal lines when the BCU break trigger event occurred.
Page 424 TC1784 On-Chip System Buses and Bus Bridges Field Bits Type Description FPIWR FPI Bus Write Indication Status This bit indicates the write signal status captured from the FPI Bus signal lines when the BCU break trigger event occurred. Single write transfer or write cycle of an atomic...
Page 425 TC1784 On-Chip System Buses and Bus Bridges Field Bits Type Description FPITAG [19:16] rh FPI Bus Master TAG Status This bit field indicates the master TAG captured from the FPI Bus signal lines when the BCU break trigger event occurred (see Table 4-15).
Page 426: Sbcu Service Request Control Register Description
Request Set Bit [9:8], Reserved Read as 0; should be written with 0. [31:16] Note: Further details on interrupt handling and processing are described in the Interrupt Chapter of this TC1784 User´s Manual. User´s Manual 4-58 V1.1, 2011-05 Buses, V1.9...
Page 427: On Chip Bus Master Tag Assignments
TC1784 On-Chip System Buses and Bus Bridges On Chip Bus Master TAG Assignments Each master interface on the FPI Bus and on the LMB Bus is assigned to a 4-bit (FPI Bus) or 3-bit (LMB Bus) identification number, the master TAG number (see Table 4-15).
Page 428: Program Memory Unit (Pmu)
The devices of this family have at least one Program Memory Unit. This is named “PMU0”. The high-end devices can have additional PMUs which are named “PMU1”, … The TC1784 has only the PMU0. The PMU0 contains the following submodules: •...
Page 429 TC1784 Program Memory Unit (PMU) To/From Local Memory Bus LMB Interface PMU0 Slave Overlay RAM Interface Control ROM Control OVRAM Flash Interface Module BROM DFLASH Emulation PFLASH Memory Interface Emulation Memory PMU0_BasicBlockDiag _generic (ED chip only ) Figure 5-1 PMU0 Basic Block Diagram User´s Manual...
Page 430: Bootrom
TC1784 Program Memory Unit (PMU) BootROM The BootROM in PMU0 has a capacity of 16 KB, organized with double-words of 64 bits. The BootROM consists basically of two parts, used for: • startup and boot SW (also called firmware), and •...
Page 431: Overlay Ram And Data Acquisition
TC1784 Program Memory Unit (PMU) Overlay RAM and Data Acquisition The overlay memory OVRAM is provided in the PMU0 especially for redirection of program memory accesses to the OVRAM by using the data overlay function. The data overlay functionality itself is controlled in the DMI module to avoid any performance penalty during the execution of redirection, and to support also external memories.
Page 432: Access Performance
TC1784 Program Memory Unit (PMU) The base address of the virtual OLDA memory range is A/8FE7 0000 (non- cached/cached space), the end address is A/8FE7 7FFF 5.2.3 Access Performance Write accesses to the PMU Overlay Memory OVRAM are performed with two cycles (because of the read-modify-write for ECC generation) for bytes, half-words and words but in one cycle for double-words.
Page 433 TC1784 Program Memory Unit (PMU) Field Bits Type Description POLDAEN Protection Bit for OLDAEN Bit protection: Bit OLDAEN remains unchanged with register OVRCON write OLDAEN can be changed with current write access to register OVRCON This bit enables OLDAEN write during OVRCON write.
Page 434: Emulation Memory Interface
(byte, half-word, word, double-word). CPU- controlled Load-Modify-Store accesses (with LDMST instruction) are not supported. In the TC1784 production device, the EMEM interface is always disabled. A CPU read access from the Emulation Memory region causes a DSE trap and an LMB bus error. If the Emulation Memory region read access is initiated by a SPB master (e.g.
Page 435: Pmu Id Register
TC1784 Program Memory Unit (PMU) PMU ID Register The PMU_ID register is a read-only register, thus write accesses lead to a bus error trap. Read accesses are permitted in Supervisor Mode SV and in User Mode. The PMU_ID register is defined as follows:...
Page 436: Tuning Protection
TC1784 Program Memory Unit (PMU) Tuning Protection The special tuning protection support represents a security function provided additionally to Flash read/write/OTP protection (see Page 5-21 Chapter 5.6.5) and additionally to the Alternate Boot Mode (see BootROM spec). For details on the tuning protection please contact your Infineon representative.
Page 437: Program And Data Flash
This chapter describes the embedded Flash module of the TC1784. 5.6.1 Introduction The embedded Flash module of TC1784 includes 2.5 MB of Flash memory for code or constant data (called Program Flash) and 128 Kbyte of additional Flash memory used for emulation of EEPROM data (called Data Flash).
Page 438 TC1784 Program Memory Unit (PMU) Redundancy Control Control Voltage Control Flash Command Control SFRs State Machine FCS FSRAM Microcode Address Addr Bus Page Write Program Buffers Flash Write Bus 256 byte WR_DATA 128 byte PF-Read ECC Code ECC Block Bank 0...
Page 439 TC1784 Program Memory Unit (PMU) • User controlled configuration blocks (UCB) in configuration sector for keywords and for sector-specific lock bits (one block for every user; up to three users). • Pad supply voltage also used for program and erase (no VPP pin).
Page 440 TC1784 Program Memory Unit (PMU) • Other characteristics: Same as Program Flash. 1) This number of cycles requires a specific robust EEPROM emulation algorithm as described in Section 5.6.6.3. User´s Manual 5-13 V1.1, 2011-05 PMU, V1.47...
Page 441: Architectural And Operational Overview
TC1784 Program Memory Unit (PMU) 5.6.2 Architectural and Operational Overview In the following, an overview of the internal structure and of operations is presented. 5.6.2.1 Sector and Page Architecture The Program Flash as well as the Data Flash memory are characterized by their sector architecture and by their page structure.
Page 442: Data Flash And Eeprom Emulation
TC1784 Program Memory Unit (PMU) times before refreshing the 64K sector. In total, also for each logical sector the max. number of erase cycles is 1000. Erase of the 64K physical sector can be performed with one 64K erase operation or with four 16K erase operations.
Page 443 TC1784 Program Memory Unit (PMU) buffer becomes the active EEPROM region. The “old” DFLASH bank can be erased, when the active EEPROM region has been switched to the “new” DFLASH bank. As a result of the continuously changing assignment of the active EEPROM region in a...
Page 444: Operational Overview
TC1784 Program Memory Unit (PMU) 5.6.2.3 Operational Overview In general, the operations of Program Flash and Data Flash are controlled identically. Therefore, in the following, the operational overview is mainly presented only for the Program Flash. When necessary, additional explanations are made for the Data Flash.
Page 445 TC1784 Program Memory Unit (PMU) to protect against inadvertent writes. Some commands which do not directly control Flash array operations are implemented as single cycle commands. All command cycles are write (store) cycles to the Flash. During command cycles, the low order 16 bits of the address bus (A15–A0) define the Flash command address, and...
Page 446 TC1784 Program Memory Unit (PMU) 2. Execute 32 (Data Flash: 16) ‘Load Page’ commands to transfer double-words or execute 64(32) commands to transfer words to the respective page assembly buffer. Mixed transfers of words and double-words are not allowed (error indication). The first double-word is loaded into the page assembly buffer to the location with address zero (starting address of page register).
Page 447 TC1784 Program Memory Unit (PMU) If the Flash bank, which is addressed, is still busy, the command cycle stall the bus system and the sending master. After the last cycle of the command sequence, the device automatically starts and controls the erase procedure. Start of operation is delayed, if another bank is busy with a write operation at that time.
Page 448 TC1784 Program Memory Unit (PMU) written by user code accessed from Program Flash. In Data Flash, also parallel write operations (programming one bank while erasing the other bank) are possible. Register Access Control Register accesses for polling the status register are allowed in any state, also during erase and program operations (but then executed out of other internal or external memory).
Page 449 TC1784 Program Memory Unit (PMU) and sectors that are protected only by user 1. User 1 can change sectors that are protected only by him but not sectors that are protected by user 0 or user 2. As for read protection, also for short-term disablement of sector write protection a password checking feature is provided.
Page 450 TC1784 Program Memory Unit (PMU) sleep state is requested, all active or pending Flash array operations are at first correctly terminated, and only then the power down state is taken. The wakeup from sleep ramps up the voltage generators, before the Flash read mode is activated again.
Page 451: Flash Access Control And Performance
TC1784 Program Memory Unit (PMU) 5.6.2.4 Flash Access Control and Performance The required number of wait states for an initial access to PFlash or DFlash is related to the maximum operating frequency (including PLL jitter). Because the default after reset is a worst case setting sufficient for all frequencies, the access times have to be configured by the user according to the application’s frequency for optimum...
Page 452 TC1784 Program Memory Unit (PMU) Table 5-2 Selection of Wait States in Relation to Operating Frequency for Flash modules with Ta=50 ns (cont’d) Operating Frequency WS for WS for WS for Initial Read Buffer Prefetch Access Hit Access Line Hit 99 MHz <...
Page 453: Functional Description
TC1784 Program Memory Unit (PMU) 5.6.3 Functional Description In the following chapters, the detailed Flash functions and the related user interface are described. 5.6.3.1 Address Mapping The total address range of 4 Gbyte (addresses A31–A0) is divided into 16 segments of each 256 Mbyte, which are addressed by A31–A28.
Page 454 TC1784 Program Memory Unit (PMU) Table 5-3 Flash Memory Map and Access Control in PMU0 Range Size Start Address Access Transaction Description ment Control Control Program Flash 8000 0000 Instr. Access 4x64-bit into cached space Mbyte via LMB PMI cache,...
Page 455: Basic Operating Modes
TC1784 Program Memory Unit (PMU) 5.6.3.2 Basic Operating Modes Generally, the Flash module distinguishes two basic operating modes, the standard read mode and the command mode. Additionally to the read mode, the page mode can be activated. Since the Flash array is represented by three autonomous Flash banks, one bank of Program Flash and two banks of Data Flash, the operating modes belong to every Flash bank and can partly be active concurrently.
Page 456 TC1784 Program Memory Unit (PMU) • UCPA: User configuration page address. • SA: Sector address; base address of sector to be erased. • UCBA: User configuration block address; base address of the 1 Kbyte UC block. • UL: User protection level; the command user level is zero (master user) or one.
Page 457 TC1784 Program Memory Unit (PMU) Table 5-4 Command Sequences for Flash Control 1)2) Command Sequence Cycle Cycle Cycle Cycle Cycle Cycle Reset to Read Address .5554 Data ..xxF0 Enter Page Mode Address .5554 Data ..xx5y *)3) Load Page Address .55F0...
Page 458: Functional Command Description
TC1784 Program Memory Unit (PMU) 3) The address “55F0 ” is used for load DW (64-bit) operations and for load word (32-bit) operations with word transfer on even half of 64-bit bus. In case of word transfers, for every second word the address has to be “55F4...
Page 459 TC1784 Program Memory Unit (PMU) With this command, the ‘page mode’ is entered, indicating that the page assembly buffer is enabled to be filled up with Load Page commands, and that a program operation is in preparation. Selection between assembly buffers of Program Flash and Data Flash is performed with the nibble “y”...
Page 460 TC1784 Program Memory Unit (PMU) In case of a completely filled page assembly buffer, an overrun condition is sampled during Load Page operations. In this case, the write data causing the overflow condition are lost. The overflow condition is indicated by the sequence error flag and by an error interrupt (if enabled), but the execution of a following Write Page command is not suppressed (the page mode is not aborted).
Page 461 TC1784 Program Memory Unit (PMU) the first command cycle is acknowledged with a retry request. After start of program operation also the BUSY flag for the addressed bank is set in FSR. The start of program operation can be delayed: •...
Page 462 TC1784 Program Memory Unit (PMU) confirmation code in the respective UC page, the new protection configuration is valid and active after the next reset. If the protection configuration in an UC block has to be re-programmed (not possible for UCB2), at first the user’s protection must be disabled and then its UC block must be erased.
Page 463 TC1784 Program Memory Unit (PMU) The sector erase algorithm includes an erase quality check that identifies incorrect erased bits in the Flash sector. If re-erasing of weak bits or soft re-programming of over- erased bits is unsuccessful, the verify error flag FSR.VER is set (see Chapter 5.6.6.3).
Page 464 TC1784 Program Memory Unit (PMU) If the Erase Phys Sector operation is used to erase a physical 64K sector of Program Flash (including the 16K sectors), this operation is only executed, if none of its 16K sectors is write protected or if protection is disabled (user 0 and/or user 1). If write protection is not disabled, or if one or more of the included 16K sectors are OTP protected, the erase operation is not started, and the protection error flag PROER is set.
Page 465 TC1784 Program Memory Unit (PMU) Disable Sector Write Protection Sector write protection of all protected sectors belonging to the user’s protection level (only in Program Flash) is temporarily disabled. This is a protected command sequence, using two user defined passwords to release this command.
Page 466 TC1784 Program Memory Unit (PMU) now supported in the PMU. The read protection control flags DCF and DDF in FCON register can now be cleared via FCON register access. The read protection (including global write protection) remains disabled until the command Resume Read/Write Protection is executed, or until the next application reset (including HW and SW reset).
Page 467: Sector, Page And Block Addressing
TC1784 Program Memory Unit (PMU) 5.6.3.5 Sector, Page and Block Addressing As all command cycles of command sequences, sector, page and block addressing as required in the command sequences shall be performed in the non-cached address space of Program Flash and Data Flash (for definition of address mapping see Table 5-3).
Page 468 TC1784 Program Memory Unit (PMU) Table 5-5 Addresses and Sizes of Sectors in Program Flash Sector Phys. Sector Sector Addresses SA Sector Range Sector Size Physical Addr. (hex) A21 – A18– A16 – A13 – 16 KB - 0 - 00’0000 –...
Page 469 TC1784 Program Memory Unit (PMU) proper A31–A22 address bits according to the mapping of Program Flash memory. Both Data Flash sectors (DS0 and DS1) and the two PFlash sectors (PS0 and PS4), as used in the command sequence ‘Erase Phys Sector’ (see...
Page 470: Register Addresses And Access Restrictions
TC1784 Program Memory Unit (PMU) Table 5-7 Addresses and Sizes of Pages (cont’d) Page Page Page Addresses PA Page Range Number Size Physical Addr. A21– A15– A11– A6– (hex) Data Flash DPneven 128 Byte Base=0 b XXXX - 0 - x’xx00 – x’xx7F...
Page 471 TC1784 Program Memory Unit (PMU) For Flash registers separate address spaces are reserved for each PMU (see Table 5-9). The detailed register list of PMU0 is contained in Table 5-3. Table 5-9 Registers Address Spaces of Flash Registers Module Base Address...
Page 472 TC1784 Program Memory Unit (PMU) Table 5-11 Addresses of Flash0 Registers (cont’d) Short Description Address Access Mode Reset Name Read Write FLASH0_ Flash Status Register F800 2010 U, SV BE Class3+ Page PORST 5-46 Reset FLASH0_ Flash Configuration F800 2014...
Page 473: Flash Status Definition
TC1784 Program Memory Unit (PMU) 5.6.3.7 Flash Status Definition The Flash Status Register FSR reflects the overall status of the Flash module after Reset and after reception of the different commands. Sector specific protection states are not indicated in the FSR, but in the registers PROCON0, PROCON1 and PROCON2. The status register is a read-only register.
Page 474 TC1784 Program Memory Unit (PMU) Field Bits Type Description D0BUSY Data Flash Bank 0 Busy HW-controlled status flag. DFlash0 ready, not busy; DFlash0 in read mode. DFlash0 busy; DFlash0 not in read mode. Indication of busy state of DFlash bank 0 because of active execution of program or erase operation;...
Page 475 TC1784 Program Memory Unit (PMU) Field Bits Type Description 3)4) ERASE Erase State HW-controlled status flag. There is no erase operation requested or in progress or just finished Erase operation requested (from FIM) or in action or finished. Set with last cycle of Erase command sequence, cleared with Clear Status command (if not busy) or with power-on reset.
Page 476 TC1784 Program Memory Unit (PMU) Field Bits Type Description 1)2)3) SQER Command Sequence Error No sequence error Command state machine operation unsuccessful because of improper address or command sequence. A sequence error is not indicated if the Reset to Read command aborts a command sequence.
Page 477 TC1784 Program Memory Unit (PMU) Field Bits Type Description RPROIN Read Protection Installed No read protection installed Read protection and global write protection (with or without Data Flash) is configured and correctly confirmed in the User Configuration Block 0. Supported only for the master user (user zero).
Page 478 TC1784 Program Memory Unit (PMU) Field Bits Type Description 1)5) WPRODIS0 Sector Write Protection Disabled for User 0 All protected sectors of user 0 are locked if write protection is installed All write-protected sectors of user 0 are temporarily unlocked, if not coincidently locked by user 2 or via read protection.
Page 479 TC1784 Program Memory Unit (PMU) Field Bits Type Description 17,20, Reserved Read zero, no write 27, 29 Note: The footnote numbers of FSR bits describe the specific reset conditions: 1)Cleared with application reset (class 3 reset) 2)Cleared with command “Reset to Read”...
Page 480: Flash Configuration Control
TC1784 Program Memory Unit (PMU) 5.6.3.8 Flash Configuration Control The Flash Configuration Register FCON reflects and controls the following general Flash configuration functions: • Number of wait states for Flash accesses (see also Table 5-1 for selection). • Indication of installed and active read protection.
Page 481 TC1784 Program Memory Unit (PMU) Field Bits Type Description WSPFLASH [3:0] Wait States for read access to PFlash This bitfield defines the number of wait states, which are used for an initial read access to the Program Flash memory area (see Table 5-1 for selection).
Page 482 TC1784 Program Memory Unit (PMU) Field Bits Type Description WSECDF Wait State for Error Correction of DFlash No additional wait state for error correction One additional wait state for error correction during read access to Data Flash IDLE Dynamic Flash Idle...
Page 483 TC1784 Program Memory Unit (PMU) Field Bits Type Description Disable Code Fetch from Flash Memory This bit enables/disables the code fetch from the internal Flash memory area. Once set, this bit can only be cleared when RPA=’0’. This bit is automatically set with reset and is cleared during rampup, if no RP installed, and during startup (BootROM SW) in case of internal start out of Flash.
Page 484 TC1784 Program Memory Unit (PMU) Field Bits Type Description DDFPCP Disable Data Fetch from PCP Controller This bit enables/disables the data read access to PFlash&DFlash memory via the LFI bridge (used from PCP controller). Once set, this bit can only be cleared when RPA=’0’.
Page 485 TC1784 Program Memory Unit (PMU) Field Bits Type Description EOBM End of Busy Interrupt Mask Interrupt not enabled EOB interrupt is enabled [7:5], Reserved Read/write zero [23:22] Note: The default numbers of wait states represent the slow cases. This is a general proceeding and additionally opens the possibility to execute higher frequencies without changing the configuration.
Page 486: Flash Identification Register
This bit field is C0 . It defines the module as a 32-bit module. MOD_NUMBER [31:16] r Module Number Value This bit field defines a module identification number. For the TC1784 Flash0 this number is 0062 User´s Manual 5-59 V1.1, 2011-05 PMU, V1.47...
Page 487: Error Correction And Margin Control
TC1784 Program Memory Unit (PMU) 5.6.4 Error Correction and Margin Control Error detection and correction is provided for all read accesses to Program Flash and Data Flash. The combination of error detection with the also available margin check provides an excellent verify function for Flash data safety.
Page 488: Margin Check Control
TC1784 Program Memory Unit (PMU) After an erase operation, a correct ECC code (all zero) is provided for the erased sector in the Program Flash as well as in the Data Flash. For details about handling ECC errors and other flags see Chapter 5.6.6.3.
Page 489 TC1784 Program Memory Unit (PMU) MARP Margin Control Register PFLASH (1018 Reset Value: 0000 8000 MARGIN MARGIN Field Bits Type Description MARGIN0 [1:0] PFLASH Margin Selection for Low Level Standard (default) margin High margin for 0 (low) level Reserved Reserved...
Page 490 TC1784 Program Memory Unit (PMU) MARD Margin Control Register DFLASH (101C Reset Value: 0000 8000 MARGIN MARGIN Field Bits Type Description MARGIN0 [1:0] DFLASH Margin Selection for Low Level Standard (default) margin High margin for 0 (low) level Reserved Reserved...
Page 491: Read And Write Protection
TC1784 Program Memory Unit (PMU) 5.6.5 Read and Write Protection For an overview please refer to Chapter 5.6.2.3 In general, three user levels are supported for installation of protection configuration, and three different types of protection can be assigned to the user levels as follows: 1.
Page 492 TC1784 Program Memory Unit (PMU) (e.g. start from external memory or from internal scratchpad memory after bootstrap execution). • If read protection is active and a bootstrap loader is selected by reset configuration, the execution of bootstrap loader is not suppressed because the Flash is fully protected with DCF and DDF (see above).
Page 493 TC1784 Program Memory Unit (PMU) special 32-bit confirmation (lock-) code is written into the UCB0-page2. Only this confirmation code enables the protection and thus the keywords. The confirmation write operation to the second wordline of the User Configuration Block shall be executed only after check of keyword-correctness (with command “Disable Read Protection”...
Page 494: Write And Otp Protection
TC1784 Program Memory Unit (PMU) Read protection can be combined with sector specific write protection. In this case, after execution of the command ‘Disable Read Protection’ only those sectors are unlocked for write accesses, which are not separately write protected.
Page 495: Protection Configuration Indication
TC1784 Program Memory Unit (PMU) The structure and layout of the three UC blocks is shown in Chapter 5.6.5.4 below, the command “Write User Configuration Page” is described in Chapter 5.6.3.4. With the command sequence “Disable Sector Write Protection” a short-term disablement of write protection for user 0 or user 1 is provided.
Page 496 TC1784 Program Memory Unit (PMU) The Flash Protection Configuration registers PROCONx are loaded by the FIM state machine out of the user’s configuration block directly after reset during rampup. The three PROCONx registers are read-only registers. They are defined as follows:...
Page 497 TC1784 Program Memory Unit (PMU) Field Bits Type Description S12/S13L Sectors 12 and 13 Locked for Write Protection by User 0 This bit is only used if PFLASH has more than 1 Mbyte. It indicates whether PFLASH sectors 12+13 (together 512 KB) are write-protected by user 0 or not.
Page 498 TC1784 Program Memory Unit (PMU) Field Bits Type Description DFEXPRO Data Flash Excluded from Read Protection When read protection is configured this bit indicates whether the DFLASH shall be excluded from read protection and global write protection or not. Attention: Even when the corresponding bit in...
Page 499 TC1784 Program Memory Unit (PMU) Field Bits Type Description SnL (n=0-9) Sector n Locked for Write Protection by User 1 These bits indicate whether PFLASH sector n is write-protected by user 1 or not. No write protection is configured for sector n.
Page 500 TC1784 Program Memory Unit (PMU) Field Bits Type Description S16/S17L Sectors 16 and 17 Locked for Write Protection by User 1 This bit is only used if PFLASH has more than 2 Mbyte. It indicates whether PFLASH sectors 16+17 (together 512 KB) are write-protected by user 1 or not.
Page 501 TC1784 Program Memory Unit (PMU) Field Bits Type Description SnROM (n=0- Sector n Locked Forever by User 2 These bits indicate whether PFLASH sector n is an OTP protected sector with read-only functionality, thus if it is locked for ever.
Page 502 TC1784 Program Memory Unit (PMU) Field Bits Type Description S16/S17ROM Sectors 16 and 17 Locked Forever by User 2 This bit is only used if PFLASH has more than 2 Mbyte. It indicates whether PFLASH sectors 16+17 (together 512 KB) are read-only sectors or not.
Page 503: User Configuration Blocks And
TC1784 Program Memory Unit (PMU) 5.6.5.4 User Configuration Blocks and Pages In the User Configuration Pages, the installation of read and write protection is configured and confirmed by the user. Three UC blocks of each 1 Kbyte are provided for three different users.
Page 504 TC1784 Program Memory Unit (PMU) Page 5-93. These bits are not reflected in the PROCON1 register, therefore their correct content can’t be verified. • The keywords are the keywords from user 1 User Configuration Block UCB2 • The UC Page 0 (bytes 255–0) of UCB2 includes the following information –...
Page 505: Interrupt, Error And Operation Control
TC1784 Program Memory Unit (PMU) 5.6.6 Interrupt, Error and Operation Control Access and/or operational errors (e.g. wrong command sequences) may be reported to the user by interrupts, and they are indicated by flags in the Flash Status Register FSR. Additionally, bus errors may be generated resulting in CPU traps (also shortly called bus error traps, although this is not correct).
Page 506: Handling Errors During Operation
TC1784 Program Memory Unit (PMU) • Not correctable double-bit error of 64-bit read data from PFlash or DFlash (if not disabled for margin check) • Not allowed write access to read only register (see Table 5-11) • Not allowed write access to ENDINIT protected register (see...
Page 507 TC1784 Program Memory Unit (PMU) • Byte transfer to password or data. • “Clear Status” or “Reset to Read” while busy • “Erase Sector” command to DFlash. • Erase UCB with wrong UCBA. New state: Read mode is entered with following exceptions: •...
Page 508 TC1784 Program Memory Unit (PMU) and the sector can not be erased (e.g. in Flash EEPROM emulation) the wordline could be invalidated if needed by marking it with all-one data and the data could be programmed to another empty wordline.
Page 509 TC1784 Program Memory Unit (PMU) be caused by programming a page whose sector was not erased correctly (e.g. aborted erase due to power failure). Under correct operating conditions a VER after programming will practically not occur. A VER after erasing is not unusual.
Page 510 TC1784 Program Memory Unit (PMU) No state change. Just the bit is set. Proposed handling by software: This flag can be used to analyze the state of the Flash memory. During normal operation it should be ignored. In order to count single-bit errors it must be cleared by “Clear Status”...
Page 511: Handling Errors During Startup
(e.g. by identifying old data by version counters). For the TC1784 this robust EEPROM algorithm is required for the usage of the DFlash. Due to the specificity of each application the appropriate usage and implementation of these measures (together with the more elaborate VER handling) must be chosen according to the context of the application.
Page 512 TC1784 Program Memory Unit (PMU) Warning Level These conditions inform the user software about an internally corrected or past error condition. Logical sector corrected: FSR bits set: VER. The Flash detected that a logical sector erase was apparently aborted by reset or power failure.
Page 513: Application Hints And Guidelines
TC1784 Program Memory Unit (PMU) 5.6.6.5 Application Hints and Guidelines Every command execution is started with the last command cycle of the command sequence, and it is indicated by the busy bit of Program Flash or Data Flash in the status register FSR.
Page 514 TC1784 Program Memory Unit (PMU) program memory, e.g. in the scratchpad SPRAM, or in the other Flash module. But user code, that writes command sequences to the Data Flash, can be located in and executed from the Program Flash in the same Flash module.
Page 515 TC1784 Program Memory Unit (PMU) checkerboard pattern. Always four sequential pages must then be programmed as follows: Page 0 with all ones, page 1 remains erased (all zeros), page 2 remains erased (all zeros), page 3 is programmed with all ones. Identically the next four pages are treated, and so on.
Page 516: Power Supply And Reset
TC1784 Program Memory Unit (PMU) 5.6.7 Power Supply and Reset The following chapters describe the required power supplies, the power consumption and its possible reduction, the control of Flash Sleep Mode and the basic control of Reset. 5.6.7.1 Power Supply...
Page 517 TC1784 Program Memory Unit (PMU) Note: The wake-up time is documented in the data sheet. This time may fully delay the interrupt response time in sleep mode. User´s Manual 5-90 V1.1, 2011-05 PMU, V1.47...
Page 518: Reset Control
TC1784 Program Memory Unit (PMU) 5.6.7.4 Reset Control The PMU-part of Flash module (FIM) uses • the application reset (“class 3 reset”), which may include all reset sources (power-on, HW, SW and watchdog reset, if configured), and • the power-on reset.
Page 519 TC1784 Program Memory Unit (PMU) The detection of aborted programming processes can be handled similarly. After programming a block of data an additional page is programmed as marker. When after reset the block of data is readable and the marker is existent it is ensured that the block of data was programmed without interruption.
Page 520 TC1784 Program Memory Unit (PMU) a) If the marker is erased the data part could have been programmed incompletely. Therefore the data part should not be used or alternatively it could be programmed again to a following page. b) If the marker contains incorrect data the data part was most likely programmed correctly but the marker was programmed incompletely.
Page 521 The same with bits 4-7 for physical sector PS4. When the ALSE repair algorithm is not needed it is recommended to switch if off completely by configuring the ALSEDIS to FF The ALSEDIS feature is only available in the TC1784 from µCode version V1.2 on. User´s Manual 5-94 V1.1, 2011-05...
Page 522: Data Access Overlay (Ovc)
TC1784 Data Access Overlay (OVC) Data Access Overlay (OVC) The data overlay functionality provides the capability to redirect data accesses by the TriCore to program memory (segments 8 and A ) called “target memory” to a different memory called “overlay memory”.
Page 523 Redirection of Data Accesses to/from Code Memory to Internal OVRAM or to Emulation Memory (or to External Memory) In the TC1784, the target memory (Program Flash, external memory or OLDA range, see Chapter 6.4.1) can be divided into a maximum of sixteen memory blocks for redirection into an overlay memory.
Page 524 TC1784 Data Access Overlay (OVC) Original Data (Target) Address 4 Bits 28 Bits Offset OMASKx 0000 11111 ..111111111 0 0000 Programmable no match match Compare OTARx TBASE 0000 RABRx OBASE 0000 Redirected 13 Bits (8 KB OVRAM) Address OBASE...
Page 525: Online Data Acquisition (Olda) And Its Overlay
TC1784 Data Access Overlay (OVC) n=0-7. The start address of the block can be an integer multiple of the programmed block size (natural page boundary). If the data segment address is A or 8 , the segment offset of the original data address is compared with the target base addresses of all overlay blocks which are enabled in RABRx.
Page 526: Target And Overlay Memories
TC1784 Data Access Overlay (OVC) functionality to the single enable bits in the 16 block control registers (RABRx) provide compatibility to enable-control in TC1766/96. • One common overlay start bit (OVSTRT) to enable all prepared (enabled) overlay configurations by writing all shadow enable bits into the 16 block control registers in parallel (write-only bit);...
Page 527: Emulation Overlay Memory
TC1784 Data Access Overlay (OVC) zero. During address translation, the upper 19 address bits are set to A/8FE8 using the same segment address as the original data (target) address. For internal overlay, the size of the overlay blocks can be 2 x 16 B, with n = 0 to 7 (16 byte to 2 Kbyte).
Page 528: Block Priority And Access Performance
TC1784 Data Access Overlay (OVC) Note: The Overlay Control does not prevent configuring the translation logic incorrectly so that memory accesses are translated to not implemented or forbidden memory ranges. Block Priority and Access Performance If concurrent matches in more than one enabled overlay block occur, the block with the lowest order number will win and perform the address translation.
Page 529 TC1784 Data Access Overlay (OVC) Table 6-2 Registers Overview Register Register Long Name Offset Access Descript- Short Address Mode ion see Name Read Write OTARx Overlay Target Address Register x 0024 U, SV SV Page 6-9 x ∗ C (x = 0-15)
Page 530 TSEG [31:28] rw Target Segment (reserved) This bit field is reserved for future use, to select a segment. In TC1784 implementation, any access to segments 8 , or A will be checked for a valid base address; return 0 if read; should be written with 0.
Page 531 TSEG [31:28] rw Target Segment (reserved) This bit field is reserved for future use, to select a segment. In TC1784 implementation, any access to segments 8 , or A will be checked for a valid base address; return 0 if read; should be written with 0.
Page 532 TC1784 Data Access Overlay (OVC) If RABRx.IEMS=0, the RABRx register is defined as follows. RABRx (x=0-15) Redirected Address Base Register x +x*C Reset Value: 0FE8 0000 IEMS RC1 RC0 FIXVAL OBASE Field Bits Type Description OBASE [12:4] Overlay Block Base Address This bit field holds the base address of the overlay memory block in the overlay memory OVRAM.
Page 533 TC1784 Data Access Overlay (OVC) Field Bits Type Description OVEN Overlay Enabled This bit controls whether or not the overlay function of overlay block x is enabled. Overlay function of block x is disabled. Overlay function of block x is enabled.
Page 534 TC1784 Data Access Overlay (OVC) If RABRx.IEMS=1 and RABRx.EXOMS=0, the RABRx register is defined as follows. The reset value is meaningless in this case because after reset the register has always the layout defined on Page 6-11. RABRx (x=0-15) Redirected Address Base Register x...
Page 535 TC1784 Data Access Overlay (OVC) Field Bits Type Description IEMS Internal or Emulation/External Memory Select IEMS selects the type of the overlay memory and the size-range of overlay blocks. Internal OVRAM is selected as overlay memory. Block sizes are 2 Bytes, n = 4-11.
Page 536 TC1784 Data Access Overlay (OVC) If RABRx.IEMS=1 and RABRx.EXOMS=1, the RABRx register is defined as follows. The reset value is meaningless in this case because after reset the register has always the layout defined on Page 6-11. RABRx (x=0-15) Redirected Address Base Register x...
Page 537 TC1784 Data Access Overlay (OVC) Field Bits Type Description IEMS Internal or Emulation/External Memory Select IEMS selects the type of the overlay memory and the size-range of overlay blocks. Internal OVRAM is selected as overlay memory. Block sizes are 2 Bytes, n = 4-11.
Page 538 TC1784 Data Access Overlay (OVC) Field Bits Type Description OMASK [10:4] Overlay Address Mask This bitfield determines the overlay block size in OVRAM and the bits used for address comparison and translation. Selectable overlay memory block sizes in OVRAM: 0000000...
Page 539 TC1784 Data Access Overlay (OVC) OMASKx (x=0-15) Overlay Mask Register x +x*C Reset Value: 0FFF FC00 OMASK Field Bits Type Description OMASK [16:10] rw Overlay Address Mask This bitfield determines the overlay block size in EMEM or in external memory (if EXOMS=1) and the bits used for address comparison and translation.
Page 540 TC1784 Data Access Overlay (OVC) Field Bits Type Description [27:17] r Fixed “1” Values Corresponding address bits are participating in the address comparison. Corresponding final address bits are taken from RABR. [9:0], Fixed “0” Values [31:28] Corresponding address bits are not used in the address comparison.
Page 541 TC1784 Data Access Overlay (OVC) The Overlay Control Register OCON is defined as follows: OCON Overlay Control Register (00E0 Reset Value: 0000 0000 SHOVENx Field Bits Type Description SHOVENx Shadow Overlay Enable x (x=0-15) Overlay block x is disabled with next OVSTRT...
Page 542 TC1784 Data Access Overlay (OVC) Field Bits Type Description DCINVAL Data Cache Invalidate No function in devices without without data cache in Tricore. No action Data Cache Lines in DMI are invalidated (flushed). Note: Per write modified cache lines are not invalidated.
Page 543: Bootrom Content
SSW-execution (the last reset event); • information stored into Flash Configuration Sector. After SSW the TC1784 executes user code out of an on-chip program memory. The initial code source can be selected via hardware configuration (i.e. defined levels on specific pins: •...
Page 544: Internal Start
- the flag is set to the inverted value of SCU_STSTAT.LUDIS bit Internal Start This is the basic TC1784 type of operation in which the user code is started out of the Internal Flash Memory. The User Start Address STADD is set to the beginning of Internal Flash Memory Module at address A000’0000...
Page 545: Bootstrap Loading
TC1784 BootROM Content – SPRAM upon a Bootstrap Loader mode • the user code configures and activates the EBU • a jump is performed to the desired location in External memory Bootstrap Loading Different Bootstrap Loader routines are used in these modes to download code/data into the Instruction Scratchpad Memory SPRAM (PMI) The selected Bootstrap Loader is executed only if the SSW-flag “Reset Configuration...
Page 546: Asc Bootstrap Loader
The ASC Bootloading routine implements the following steps: • RxD/TxD pins configuration is done in accordance to the TC1784 definitions, as well as depending either the routine is invoked upon “ASC Bootloader”-startup mode (ASC-only pins are used) or following an ASC-protocol detection upon “Generic Bootloader”-mode (CAN/ASC-shared pins are used but configured to ASC module)
Page 547: Can Bootstrap Loader
(5555 ) and the baud rate registers of the MultiCAN module are set accordingly. The TC1784 is now ready to receive CAN frames with the baud rate of the external host. Acknowledge Phase In the acknowledge phase, the bootstrap loader waits until it receives the next correctly recognized initialization frame from the external host, and acknowledges this frame by generating a dominant bit in its ACK slot.
Page 548: Alternate Boot Modes
ABM Headers. In any Alternate Boot Mode of TC1784 two such Headers are defined - Header 0 and Header 1 (referred as ABM.HD0 and ABM.HD1), respectively user code can be started from up to two different start addresses.
Page 549 = x +x+1 (7.1) This calculation is performed by the SSW using the Memory Checker Module in TC1784. The complete check-procedure for a Header consists of the following steps: 1. check the ABM Header ID at offsets 04 ..07...
Page 550 TC1784 BootROM Content b) inverse the result value and compare with CRChead (offset 1C - if OK - continue with 3. - if Not - exit the check-procedure for this Header with Error. 3. calculate the CRC over the memory address range ChkStart...ChkEnd (start- and...
Page 551: Startup Errors Handling
Respectively, a second WDT reset will occur being already a locked reset, which can be aborted only by a next power-on sequence. Table 7-3 Errors reported by the TC1784 SSW Coding in Description d12/COMDATA...
Page 552: Notes And Usage Hints
Watchdog-Timer - running in time-out mode 7.7.2 RAMs Handling No RAM initialization is performed by the Startup Software in TC1784. The user should take care, if ECC Control will be enabled for a RAM module, first to assure a correct initial content of this memory.
Page 553: Memory Maps
Memory Maps Memory Maps This chapter gives an overview of the TC1784 memory map, and describes the address locations and access possibilities for the units, memories, and reserved areas as “seen” from the two different on-chip buses’ point of view.
Page 554: What Is New
AudoNG and AudoFuture. Major differences of the TC1784 Memory Map compared to AudoNG: • Address map is adapted to the peripheral set of the products (peripherals where added/removed, number of ports is adapted).
Page 555: How To Read The Address Maps
TC1784 Memory Maps How to Read the Address Maps The bus-specific address maps describe how the different bus master devices react on accesses to on-chip memories and modules, and which address ranges are valid or invalid for the corresponding buses.
Page 556 TC1784 Memory Maps Table 8-1 defines the acronyms and other terms that are used in the address maps (Table 8-2 Table 8-4). Table 8-1 Definition of Acronyms and Terms Term Description …BE Means “Bus error” generation. …BET Means “Bus error & trap” generation.
Page 557: Contents Of The Segments
Contents of the Segments This section summarizes the contents of the segments. Segments 0-7 These segments are reserved segments in the TC1784. Segment 8 From the SPB point of view (PCP), this memory segment allows accesses to all PMU memories (PFLASH, DFLASH, EBU, BROM, TROM and OVRAM).
Page 558 TC1784 Memory Maps From the LMB point of view (CPU-PMI, CPU-DMI, DMA including. Cerberus and MLI), this memory segment allows non-cached accesses to the PMI scratch-pad RAM (SPRAM). From the DMA point of view, Move Engine, Cerberus and MLI accesses to this segment are processed by the DMA LMB master interface on the LMB Bus.
Page 559: Address Map Of The Fpi Bus System
TC1784 Memory Maps Address Map of the FPI Bus System This chapter describes the system address map from FPI Bus (SPB) point of view. 8.4.1 Segments 0 to 14 Table 8-2 shows the address map of segments 0 to 14 as it is seen from the SPB bus masters PCP, DMA and OCDS.
Page 560 Range Read Write 8FE8 2000 – Reserved LMBBE & LMBBE 8FEF FFFF SPBBE 8FF0 0000 512 Kbyte Reserved for TC1784 SPBBE SPBBE 8FF7 FFFF emulation device memory 8FF8 0000 – Reserved SPBBE SPBBE 8FFF BFFF 8FFF C000 16 Kbyte...
Page 561 SPB Address Map of Segment 0 to 14 (cont’d) Seg- Address Size Description Access Type ment Range Read Write AFF0 0000 512 Kbyte Reserved for TC1784 LMBBE & LMBBE AFF7 FFFF emulation device SPBBE memory AFF8 0000 – Reserved LMBBE & LMBBE...
Page 562 TC1784 Memory Maps Table 8-2 SPB Address Map of Segment 0 to 14 (cont’d) Seg- Address Size Description Access Type ment Range Read Write D400 0000 24 Kbyte PMI Scratch-Pad RAM access access D400 5FFF (SPRAM) D400 6000 8 Kbyte...
Page 563 TC1784 Memory Maps Table 8-2 SPB Address Map of Segment 0 to 14 (cont’d) Seg- Address Size Description Access Type ment Range Read Write E850 0000 24 Kbyte PMI Scratch-Pad RAM access access E850 5FFF (SPRAM) E850 6000 8 Kbyte...
Page 564: Segment 15
TC1784 Memory Maps 8.4.2 Segment 15 Table 8-3 shows the address map of segment 15 as seen from the SPB bus masters PCP, DMA and OCDS. Please note that access in Table 8-3 means only that an access to an address within the defined address range is not automatically incorrect or ignored.
Page 565 TC1784 Memory Maps Table 8-3 SPB Address Map of Segment 15 (cont’d) Unit Address Size Access Type Range Read Write Port 3 F000 0F00 access access F000 0FFF byte Port 4 F000 1000 access access F000 10FF byte Port 5...
Page 566 TC1784 Memory Maps Table 8-3 SPB Address Map of Segment 15 (cont’d) Unit Address Size Access Type Range Read Write Reserved F000 3600 – SPBBE SPBBE F000 37FF Reserved F000 3800 – SPBBE SPBBE F000 3BFF 3 × 256 Direct Memory Access Controller...
Page 567 TC1784 Memory Maps Table 8-3 SPB Address Map of Segment 15 (cont’d) Unit Address Size Access Type Range Read Write Reserved F010 0000 SPBBE SPBBE F010 00FF Synchronous Serial Interface 0 F010 0100 access access (SSC0) F010 01FF byte Synchronous Serial Interface 1...
Page 568 TC1784 Memory Maps Table 8-3 SPB Address Map of Segment 15 (cont’d) Unit Address Size Access Type Range Read Write 4 × 64 MLI0 Large Transfer Windows F020 0000 access access F023FFFF Kbyte Reserved F024 0000 SPBBE SPBBE F02F FFFF...
Page 569 TC1784 Memory Maps Table 8-3 SPB Address Map of Segment 15 (cont’d) Unit Address Size Access Type Range Read Write Reserved F800 0400 – LMBBE & LMBBE F800 04FF SPBBE Program Memory Unit (PMU) F800 0500 access access F800 05FF...
Page 570: Address Map Of The Local Memory Bus (Lmb)
Overlay memory access access 8FE8 1FFF (OVRAM) 8FE8 2000 – Reserved LMBBET LMBBET 8FEF FFFF 8FF0 0000 512 Kbyte Reserved for TC1784 LMBBET LMBBET 8FF7 FFFF emulation device memory 8FF8 0000 – Reserved LMBBET LMBBET 8FFF BFFF User´s Manual 8-18 V1.1, 2011-05...
Page 571 Overlay memory access access AFE8 1FFF (OVRAM) AFE8 2000 – Reserved LMBBET LMBBET AFEF FFFF AFF0 0000 512 Kbyte Reserved for TC1784 LMBBET LMBBET AFF7 FFFF emulation device memory AFF8 0000 – Reserved LMBBET LMBBET AFFF BFFF AFFF C000 16 Kbyte...
Page 572 TC1784 Memory Maps Table 8-4 LMB Address Map (cont’d) Seg- Address Size Description Action ment Range Read Write B000 0000 Reserved SPBBET SPBBE BFFF FFFF Mbyte C000 0000 24 Kbyte PMI Scratch-Pad RAM access access C000 5FFF (SPRAM) C000 6000...
Page 573 TC1784 Memory Maps Table 8-4 LMB Address Map (cont’d) Seg- Address Size Description Action ment Range Read Write D400 0000 24 Kbyte PMI Scratch-Pad RAM access access D400 5FFF (SPRAM) D400 6000 8 Kbyte access access D400 7FFF D400 8000...
Page 574 TC1784 Memory Maps Table 8-4 LMB Address Map (cont’d) Seg- Address Size Description Action ment Range Read Write F800 1000 5 Kbyte Flash Registers (PMU) access access F800 23FF ≈ 8 Mbyte Reserved F800 2400 LMBBET LMBBET F87F FAFF F87F FB00...
Page 575: Memory Module Access Restrictions
TC1784 Memory Maps Memory Module Access Restrictions Table 8-5 describes which type of accesses are possible to the different memories in the TC1784. Table 8-5 Possible Memory Accesses Memory Byte Half-word Word Double-word SPRAM LDRAM – – – – –...
Page 576: Side Effects From Modules To Ldram
TC1784 Memory Maps Side Effects from Modules to LDRAM Please note that the LDRAM is also used by Boot routine and can be used by the CPU for system tasks: • the Boot routine copies some devices informations during the startup into the LDRAM (see chapter ´BootROM Content´)
Page 577: General Purpose I/O Ports And Peripheral I/O Lines (Ports)
General Purpose I/O Ports and Peripheral I/O Lines (Ports) General Purpose I/O Ports and Peripheral I/O Lines (Ports) The TC1784 has 126 digital general purpose input/output (GPIO) port lines which are connected to the on-chip peripheral units. Basic Port Operation Figure 9-1 shows a general block diagram of a TC1784 GPIO port line.
Page 578: Description Scheme For The Port Io Functions
TC1784 General Purpose I/O Ports and Peripheral I/O Lines (Ports) 9.1.1 Description Scheme for the Port IO Functions The following general building block is used to describe each GPIO pin: Table 9-1 Port x Input/Output Functions Port Select Connected Signal(s) From / to Module Px.y...
Page 579: Description Of The Port Operation
TC1784 General Purpose I/O Ports and Peripheral I/O Lines (Ports) – ENx - the pins in one port having the same ENx (x=0, 1, 2, ...), are controlled as a group by a dedicated HW_EN signal. – SEN - Single EN - the pin is controlled by its own, dedicated, single HW_EN signal •...
Page 580 Pn_IN. All GPIO lines of the TC1784 that are used by the GPTA module have an emergency stop logic. This logic makes it possible to individually disconnect GPTA outputs from the driving GPTA module outputs and to put them onto a well defined logic state in an emergency case.
Page 581: Port Register Description
TC1784 General Purpose I/O Ports and Peripheral I/O Lines (Ports) Port Register Description The individual control and data bits of each GPIO port are implemented in a number of registers. The registers are used to configure the port as general-purpose I/O or alternate function input/output.
Page 582 TC1784 General Purpose I/O Ports and Peripheral I/O Lines (Ports) Table 9-3 Registers Address Space Module Base Address End Address Note F000 1300 F000 13FF 16-bit F000 1400 F000 14FF 15-bit F000 1500 F000 15FF 9-bit F000 1600 F000 16FF...
Page 583 TC1784 General Purpose I/O Ports and Peripheral I/O Lines (Ports) Register Access Rights and Reset Class Table 9-5 Registers Access Rights and Reset Classes Register Short Name Access Rights Reset Class Read Write Pn_OUT U,SV U,SV Class 3 Pn_OMR Pn_IOCR0...
Page 584: Port Input/Output Control Registers
TC1784 General Purpose I/O Ports and Peripheral I/O Lines (Ports) 9.2.1 Port Input/Output Control Registers The port input/output control registers select the digital output and input driver functionality and characteristics of a GPIO port pin. Port direction (input or output), pull- up or pull-down devices for inputs, and push-pull or open-drain functionality for outputs can be selected by the corresponding bit fields PCx (x = 0-15).
Page 585 TC1784 General Purpose I/O Ports and Peripheral I/O Lines (Ports) Pn_IOCR4 (n=0-3) Port n Input/Output Control Register 4 (F000 0C14 +n*100 Reset Value: 2020 2020 P5_IOCR4 Port n Input/Output Control Register 4 Reset Value: 2020 2020 Pn_IOCR4 (n=7-10) Port n Input/Output Control Register 4...
Page 586 TC1784 General Purpose I/O Ports and Peripheral I/O Lines (Ports) Pn_IOCR8 (n=0-2) Port n Input/Output Control Register 8 (F000 0C18 +n*100 Reset Value: 2020 2020 P3_IOCR8 Port 3 Input/Output Control Register 8 Reset Value: 2020 2020 P5_IOCR8 Port n Input/Output Control Register 8...
Page 587 TC1784 General Purpose I/O Ports and Peripheral I/O Lines (Ports) Pn_IOCR12 (n=0-2) Port n Input/Output Control Register 12 (F000 0C1C +n*100 Reset Value: 2020 2020 P3_IOCR12 Port 3 Input/Output Control Register 12 Reset Value: 2020 2020 P5_IOCR12 Port 5 Input/Output Control Register 12...
Page 588 TC1784 General Purpose I/O Ports and Peripheral I/O Lines (Ports) Port Control Coding Table 9-6 describes the coding of the PCx bit fields that determine the port line functionality. Table 9-6 PCx Coding PCx[3:0] Output Selected Pull-up/Pull-down/ Characteristics Selected Output Function...
Page 589: Pad Driver Mode Register
Pad Driver Mode Register Overview The pad structure of the TC1784 GPIO lines offers the possibility to select the output driver strength and the slew rate. These two parameters are controlled by the bit fields in the pad driver mode register Pn_PDR, independently of input/output and pull-up/pull- down control functionality as programmed in the Pn_IOCR register.
Page 590 Strong soft Strong soft Strong sharp minus Strong slow Medium Medium Medium Weak Strong medium minus Medium Weak Weak Note: See the TC1784 Data Sheet for detailed DC characteristics of class A1/2 pads. User´s Manual 9-14 V1.1, 2011-05 Ports, V1.1...
Page 591 TC1784 General Purpose I/O Ports and Peripheral I/O Lines (Ports) Pad Driver Mode Register This is the general description of the PDR register. Each port contains its own specific PDR register, described additionally at each port, that can contain between one and eight PDx fields.
Page 592: Port Output Register
TC1784 General Purpose I/O Ports and Peripheral I/O Lines (Ports) 9.2.3 Port Output Register The port output register determines the value of a GPIO pin when it is selected by Pn_IOCRx as output. Writing a 0 to a Pn_OUT.Px (x = 0-15) bit position delivers a low level at the corresponding output pin.
Page 593: Port Output Modification Register
TC1784 General Purpose I/O Ports and Peripheral I/O Lines (Ports) 9.2.4 Port Output Modification Register The port output modification register contains control bits that make it possible to individually set, reset, or toggle the logic state of a single port line by manipulating the output register.
Page 594 TC1784 General Purpose I/O Ports and Peripheral I/O Lines (Ports) Table 9-9 Function of the Bits PRx and PSx (cont’d) Function Bit Pn_OUT.Px is reset. Bit Pn_OUT.Px is toggled. User´s Manual 9-18 V1.1, 2011-05 Ports, V1.1...
Page 595: Emergency Stop Register
TC1784 General Purpose I/O Ports and Peripheral I/O Lines (Ports) 9.2.5 Emergency Stop Register All GPIO lines have an emergency stop logic (see Figure 9-1). Each GPIO line has its own emergency stop enable bit ENx that is located in the emergency stop register Pn_ESR of Port n.
Page 596: Port Input Register
TC1784 General Purpose I/O Ports and Peripheral I/O Lines (Ports) Field Bits Type Description [31:16] r Reserved Read as 0; should be written with 0. Note: Only Ports 0, 3, and 5 are 16-bit wide ports. The Pn_ESR registers of the other ports have a reduced number of bits (see Pn_ESR register descriptions in the corresponding port sections).
Page 597: Port 0
TC1784 General Purpose I/O Ports and Peripheral I/O Lines (Ports) Port 0 This section describes the Port 0 functionality in detail. 9.3.1 Port 0 Configuration Port 0 is a general-purpose 16-bit bi-directional port that can be alternatively used for the GPTA and SCU modules.
Page 598 TC1784 General Purpose I/O Ports and Peripheral I/O Lines (Ports) Table 9-10 Port 0 Functions (cont’d) Port I/O Pin Functionality Associated Reg./ Port I/O Control Select. I/O Line Reg./Bit Value Field P0.2 General-purpose input P0_IN.P2 P0_IOCR0. 0XXX GPTA input SCU input...
Page 599 TC1784 General Purpose I/O Ports and Peripheral I/O Lines (Ports) Table 9-10 Port 0 Functions (cont’d) Port I/O Pin Functionality Associated Reg./ Port I/O Control Select. I/O Line Reg./Bit Value Field P0.5 General-purpose input P0_IN.P5 P0_IOCR4. 0XXX GPTA input SCU input...
Page 600 TC1784 General Purpose I/O Ports and Peripheral I/O Lines (Ports) Table 9-10 Port 0 Functions (cont’d) Port I/O Pin Functionality Associated Reg./ Port I/O Control Select. I/O Line Reg./Bit Value Field P0.8 General-purpose input P0_IN.P8 P0_IOCR8. 0XXX GPTA input LTCA2 input...
Page 601 TC1784 General Purpose I/O Ports and Peripheral I/O Lines (Ports) Table 9-10 Port 0 Functions (cont’d) Port I/O Pin Functionality Associated Reg./ Port I/O Control Select. I/O Line Reg./Bit Value Field P0.12 I General-purpose input P0_IN.P12 P0_IOCR12. 0XXX PC12 GPTA input...
Page 602: Port 0 Registers
TC1784 General Purpose I/O Ports and Peripheral I/O Lines (Ports) 9.3.3 Port 0 Registers The following registers are available on Port 0: Table 9-11 Port 0 Registers Register Register Long Name Offset Description Short Name Address P0_OUT Port 0 Output Register...
Page 603: Port 0 Pad Driver Mode Register And Pad Classes
TC1784 General Purpose I/O Ports and Peripheral I/O Lines (Ports) 9.3.3.1 Port 0 Pad Driver Mode Register and Pad Classes The Port 0 pad driver mode register contains two bit fields that determine the pad driver mode (output driver strength and slew rate) of Port 0 line groups.
Page 604: Port 1
TC1784 General Purpose I/O Ports and Peripheral I/O Lines (Ports) Port 1 This section describes the Port 1 functionality in detail. 9.4.1 Port 1 Configuration Port 1 is a 16-bit bi-directional general-purpose I/O port that can be alternatively used for the GPTA I/O lines, SSC1 and ADC0 interfaces.
Page 605: Port 1 Function Table
TC1784 General Purpose I/O Ports and Peripheral I/O Lines (Ports) 9.4.2 Port 1 Function Table Table 9-12 summarizes the I/O control selection functions of each Port 1 line. Table 9-12 Port 1 Functions Port Pin Functionality Associated Port I/O Control Select.
Page 606 TC1784 General Purpose I/O Ports and Peripheral I/O Lines (Ports) Table 9-12 Port 1 Functions (cont’d) Port Pin Functionality Associated Port I/O Control Select. Reg./ I/O Line Reg./Bit Value Field P1.3 General-purpose input P1_IN.P3 P1_IOCR0. 0XXX GPTA input IN19 LTCA2 input...
Page 607 TC1784 General Purpose I/O Ports and Peripheral I/O Lines (Ports) Table 9-12 Port 1 Functions (cont’d) Port Pin Functionality Associated Port I/O Control Select. Reg./ I/O Line Reg./Bit Value Field P1.7 General-purpose input P1_IN.P7 P1_IOCR4. 0XXX GPTA input IN23 LTCA2 output...
Page 608 TC1784 General Purpose I/O Ports and Peripheral I/O Lines (Ports) Table 9-12 Port 1 Functions (cont’d) Port Pin Functionality Associated Port I/O Control Select. Reg./ I/O Line Reg./Bit Value Field P1.10 I General-purpose input P1_IN.P10 P1_IOCR8. 0XXX PC10 GPTA input...
Page 609 TC1784 General Purpose I/O Ports and Peripheral I/O Lines (Ports) Table 9-12 Port 1 Functions (cont’d) Port Pin Functionality Associated Port I/O Control Select. Reg./ I/O Line Reg./Bit Value Field P1.14 I General-purpose input P1_IN.P14 P1_IOCR12. 0XXX PC14 LTCA2 input...
Page 610: Port 1 Registers
TC1784 General Purpose I/O Ports and Peripheral I/O Lines (Ports) 9.4.3 Port 1 Registers The following registers are available on Port 1: Table 9-13 Port 1 Registers Register Register Long Name Offset Description Short Name Address P1_OUT Port 1 Output Register...
Page 611: Port 1 Input/Output Control Register 12
TC1784 General Purpose I/O Ports and Peripheral I/O Lines (Ports) 9.4.3.3 Port 1 Input/Output Control Register 12 Port 1 contains the register P1_IOCR12 fully implemented. 9.4.3.4 Port 1 Input Register The basic P1_IN register functionality is described on Page 9-20.
Page 612: Port 1 Emergency Stop Register
TC1784 General Purpose I/O Ports and Peripheral I/O Lines (Ports) Field Bits Type Description 3, 7, Reserved 11, 15, Read as 0; should be written with 0. [31:23] 9.4.3.6 Port 1 Emergency Stop Register The basic P1_ESR register functionality is described on Page 9-19.
Page 613: Port 2
TC1784 General Purpose I/O Ports and Peripheral I/O Lines (Ports) Port 2 This section describes the Port 2 functionality in detail. 9.5.1 Port 2 Configuration Port 2 is a 14-bit bi-directional general-purpose I/O port which can be alternatively used for GPTA I/O, and interface for MLI0, MSC0 or SSC0/1.
Page 614 TC1784 General Purpose I/O Ports and Peripheral I/O Lines (Ports) Table 9-14 Port 2 Functions (cont’d) Port I/O Pin Functionality Associated Reg./ Port I/O Control Select. I/O Line Reg./Bit Value Field P2.3 General-purpose input P2_IN.P3 P2_IOCR0. 0XXX GPTA input IN35 General-purpose output P2_OUT.P3...
Page 615 TC1784 General Purpose I/O Ports and Peripheral I/O Lines (Ports) Table 9-14 Port 2 Functions (cont’d) Port I/O Pin Functionality Associated Reg./ Port I/O Control Select. I/O Line Reg./Bit Value Field P2.7 General-purpose input P2_IN.P7 P2_IOCR4. 0XXX GPTA input IN39...
Page 616 TC1784 General Purpose I/O Ports and Peripheral I/O Lines (Ports) Table 9-14 Port 2 Functions (cont’d) Port I/O Pin Functionality Associated Reg./ Port I/O Control Select. I/O Line Reg./Bit Value Field P2.11 I General-purpose input P2_IN.P11 P2_IOCR8. 0XXX PC11 SSC1 input...
Page 617: Port 2 Registers
TC1784 General Purpose I/O Ports and Peripheral I/O Lines (Ports) 9.5.3 Port 2 Registers The following registers are available on Port 2: Table 9-15 Port 2 Registers Register Register Long Name Offset Description Short Name Address P2_OUT Port 2 Output Register...
Page 618: Port 2 Pad Driver Mode Register And Pad Classes
TC1784 General Purpose I/O Ports and Peripheral I/O Lines (Ports) 9.5.3.4 Port 2 Pad Driver Mode Register and Pad Classes The Port 2 pad driver mode register contains five bit fields that determine the pad driver mode (output driver strength and slew rate) of Port 2 line groups. The Port 2 port lines are assigned to A1 and A2 pad classes.
Page 619: Port 3
TC1784 General Purpose I/O Ports and Peripheral I/O Lines (Ports) Port 3 This section describes the Port 3 functionality in detail. 9.6.1 Port 3 Configuration Port 3 is a 16-bit bi-directional general-purpose I/O port which can be alternatively used for ASC0/1, SSC0/1 and CAN lines.
Page 620: Port 3 Function Table
TC1784 General Purpose I/O Ports and Peripheral I/O Lines (Ports) 9.6.2 Port 3 Function Table Table 9-16 summarizes the I/O control selection functions of each Port 3 line. Table 9-16 Port 3 Functions Port I/O Pin Functionality Associated Reg./ Port I/O Control Select.
Page 621 TC1784 General Purpose I/O Ports and Peripheral I/O Lines (Ports) Table 9-16 Port 3 Functions (cont’d) Port I/O Pin Functionality Associated Reg./ Port I/O Control Select. I/O Line Reg./Bit Value Field P3.3 General-purpose input P3_IN.P3 P3_IOCR0. 0XXX SSC0 input (Master Mode) MRST0 General-purpose output P3_OUT.P3...
Page 622 TC1784 General Purpose I/O Ports and Peripheral I/O Lines (Ports) Table 9-16 Port 3 Functions (cont’d) Port I/O Pin Functionality Associated Reg./ Port I/O Control Select. I/O Line Reg./Bit Value Field P3.7 General-purpose input P3_IN.P7 P3_IOCR4. 0XXX SSC0 input SLSI0 General-purpose output P3_OUT.P7...
Page 623 TC1784 General Purpose I/O Ports and Peripheral I/O Lines (Ports) Table 9-16 Port 3 Functions (cont’d) Port I/O Pin Functionality Associated Reg./ Port I/O Control Select. I/O Line Reg./Bit Value Field P3.11 I General-purpose input P3_IN.P11 P3_IOCR8. 0XXX PC11 SCU input...
Page 624 TC1784 General Purpose I/O Ports and Peripheral I/O Lines (Ports) Table 9-16 Port 3 Functions (cont’d) Port I/O Pin Functionality Associated Reg./ Port I/O Control Select. I/O Line Reg./Bit Value Field P3.14 I General-purpose input P3_IN.P14 P3_IOCR12. 0XXX PC14 CAN node 1 receive input 0 RXDCAN1...
Page 625: Port 3 Registers
TC1784 General Purpose I/O Ports and Peripheral I/O Lines (Ports) 9.6.3 Port 3 Registers The following registers are available on Port 3: Table 9-17 Port 3 Registers Register Register Long Name Offset Description Short Name Address P3_OUT Port 3 Output Register...
Page 626: Port 3 Pad Driver Mode Register And Pad Classes
TC1784 General Purpose I/O Ports and Peripheral I/O Lines (Ports) 9.6.3.1 Port 3 Pad Driver Mode Register and Pad Classes The Port 3 pad driver mode register contains six bit fields that determine the pad driver mode (output driver strength and slew rate) of Port 3 line groups.
Page 627: Port 3 Emergency Stop Register
TC1784 General Purpose I/O Ports and Peripheral I/O Lines (Ports) 9.6.3.2 Port 3 Emergency Stop Register The basic P3_ESR register functionality is described on Page 9-19. At Port 3, the port lines P3.[4:0] and P3.[15:7] are connected to GPTA I/O lines. Nevertheless, all port lines have the emergency stop feature.
Page 628: Port 4
TC1784 General Purpose I/O Ports and Peripheral I/O Lines (Ports) Port 4 This section describes the Port 4 functionality in detail. 9.7.1 Port 4 Configuration Port 4 is a 4-bit bi-directional general-purpose I/O port. 9.7.2 Port 4 Function Table Table 9-18 summarizes the I/O control selection functions of each Port 4 line.
Page 629: Port 4 Registers
TC1784 General Purpose I/O Ports and Peripheral I/O Lines (Ports) Table 9-18 Port 4 Functions (cont’d) Port I/O Pin Functionality Associated Reg./ Port I/O Control Select. I/O Line Reg./Bit Field Value P4.2 General-purpose input P4_IN.P2 P4_IOCR0.PC2 0XXX GPTA input IN30...
Page 630: Port 4 Output Register
TC1784 General Purpose I/O Ports and Peripheral I/O Lines (Ports) Note: Bit field HWCFG in register RST_SR contains the latched logic levels of the Port 4 inputs that have been detected at the last low-to-high transition of HDRST. 9.7.3.1 Port 4 Output Register...
Page 631: Port 4 Pad Driver Mode Register And Pad Classes
TC1784 General Purpose I/O Ports and Peripheral I/O Lines (Ports) 9.7.3.6 Port 4 Pad Driver Mode Register and Pad Classes The Port 4 pad driver mode register contains three bit fields that determine the pad driver mode (output driver strength and slew rate) of Port 4 lines and line groups.
Page 632: Port 5
TC1784 General Purpose I/O Ports and Peripheral I/O Lines (Ports) Port 5 This section describes the Port 5 functionality in detail. 9.8.1 Port 5 Configuration Port 5 is a 16-bit bi-directional general-purpose I/O port, used for the GPTA I/O or the MLI0 interface.
Page 633: Port 5 Function Table
TC1784 General Purpose I/O Ports and Peripheral I/O Lines (Ports) 9.8.2 Port 5 Function Table Table 9-20 summarizes the I/O control selection functions of each Port 5 line. Table 9-20 Port 5 Functions Port I/O Pin Functionality Associated Reg./ Port I/O Control Select.
Page 634 TC1784 General Purpose I/O Ports and Peripheral I/O Lines (Ports) Table 9-20 Port 5 Functions (cont’d) Port I/O Pin Functionality Associated Reg./ Port I/O Control Select. I/O Line Reg./Bit Value Field P5.3 General-purpose input P5_IN.P3 P5_IOCR0. 0XXX GPTA input IN43 General-purpose output P5_OUT.P3...
Page 635 TC1784 General Purpose I/O Ports and Peripheral I/O Lines (Ports) Table 9-20 Port 5 Functions (cont’d) Port I/O Pin Functionality Associated Reg./ Port I/O Control Select. I/O Line Reg./Bit Value Field P5.6 General-purpose input P5_IN.P6 P5_IOCR4. 0XXX GPTA input IN46...
Page 636 TC1784 General Purpose I/O Ports and Peripheral I/O Lines (Ports) Table 9-20 Port 5 Functions (cont’d) Port I/O Pin Functionality Associated Reg./ Port I/O Control Select. I/O Line Reg./Bit Value Field P5.10 I General-purpose input P5_IN.P10 P5_IOCR4. 0XXX PC10 General-purpose output P5_OUT.P10...
Page 637: Port 5 Registers
TC1784 General Purpose I/O Ports and Peripheral I/O Lines (Ports) Table 9-20 Port 5 Functions (cont’d) Port I/O Pin Functionality Associated Reg./ Port I/O Control Select. I/O Line Reg./Bit Value Field P5.15 I General-purpose input P5_IN.P15 P5_IOCR4. 0XXX PC15 ERAY input...
Page 638: Port 5 Pad Driver Mode Register And Pad Classes
TC1784 General Purpose I/O Ports and Peripheral I/O Lines (Ports) 9.8.3.2 Port 5 Pad Driver Mode Register and Pad Classes The Port 5 pad driver mode register contains four bit fields that determine the pad driver mode (output driver strength and slew rate) of Port 5 line groups.
Page 639: Port 6
Figure 9-3 Port 6 Pad Connections Note: Applicable in TC1784 A-step only, the following constraint applies to an LVDS pair used in CMOS mode: only one pin of a pair should be used as output, the other should be used as input, or both pins should be used as inputs. Using both pins as outputs is not recommended because of high crosstalk between them.
Page 640: Port 6 Registers
TC1784 General Purpose I/O Ports and Peripheral I/O Lines (Ports) 9.9.1 Port 6 Registers For this port, all pins can be read as GPIO, from the Port Input Register. Table 9-22 Port 6 Registers Register Register Long Name Address Description...
Page 641: Port 6 Functions
TC1784 General Purpose I/O Ports and Peripheral I/O Lines (Ports) 9.9.2 Port 6 Functions Port 6 is a 10-bit port. The following table describes the mapping of the pins of Port 6 and the related I/O signals. It provides, among others, LVDS/CMOS outputs of MSC0.
Page 642: Port 6 Pad Driver Mode Register
TC1784 General Purpose I/O Ports and Peripheral I/O Lines (Ports) 9.9.2.1 Port 6 Pad Driver Mode Register P6_PDR Port 6 Pad Driver Mode Register Reset Value: 0000 0000 Field Bits Type Description [2:0] Pad Driver Mode for P6.[1:0] The msb of PD0 switches between CMOS and LVDS pads.
Page 643: Port 7
TC1784 General Purpose I/O Ports and Peripheral I/O Lines (Ports) 9.10 Port 7 Port 7 is a 16-bit GPIO port with EBU functionality. 9.10.1 Port 7 Registers For this port, all pins can be read as GPIO, from the Port Input Register.
Page 644: Port 7 Functions
TC1784 General Purpose I/O Ports and Peripheral I/O Lines (Ports) 9.10.2 Port 7 Functions Port 7 is a 16-bit port with EBU functionality. The following table describes the mapping of the pins of Port 7 and the related I/O signals.
Page 645 TC1784 General Purpose I/O Ports and Peripheral I/O Lines (Ports) Table 9-25 Port 7 Functions (cont’d) Port Pin Functionality Associated Port I/O Control Select. Reg./ I/O Line Reg./Bit Value Field P7.3 General-purpose input P7_IN.P3 P7_IOCR0. 0XXX EBU input General-purpose output P7_OUT.P3...
Page 646 TC1784 General Purpose I/O Ports and Peripheral I/O Lines (Ports) Table 9-25 Port 7 Functions (cont’d) Port Pin Functionality Associated Port I/O Control Select. Reg./ I/O Line Reg./Bit Value Field P7.7 General-purpose input P7_IN.P7 P7_IOCR4. 0XXX EBU input General-purpose output P7_OUT.P7...
Page 647 TC1784 General Purpose I/O Ports and Peripheral I/O Lines (Ports) Table 9-25 Port 7 Functions (cont’d) Port Pin Functionality Associated Port I/O Control Select. Reg./ I/O Line Reg./Bit Value Field P7.11 I General-purpose input P7_IN.P11 P7_IOCR8. 0XXX PC11 EBU input...
Page 648 TC1784 General Purpose I/O Ports and Peripheral I/O Lines (Ports) Table 9-25 Port 7 Functions (cont’d) Port Pin Functionality Associated Port I/O Control Select. Reg./ I/O Line Reg./Bit Value Field P7.15 I General-purpose input P7_IN.P15 P7_IOCR12. 0XXX PC15 EBU input...
Page 649: Port 7 Pad Driver Mode Register
TC1784 General Purpose I/O Ports and Peripheral I/O Lines (Ports) 9.10.2.1 Port 7 Pad Driver Mode Register P7_PDR Port 7 Pad Driver Mode Register Reset Value: 0000 0000 Field Bits Type Description [2:0] Pad Driver Mode for P7.[3:0] (Class A2 pads; coding see...
Page 650: Port 8
TC1784 General Purpose I/O Ports and Peripheral I/O Lines (Ports) 9.11 Port 8 Port 8 is an 15-bit GPIO port with EBU functionality. 9.11.1 Port 8 Registers For this port, all pins can be read as GPIO, from the Port Input Register.
Page 651: Port 8 Functions
TC1784 General Purpose I/O Ports and Peripheral I/O Lines (Ports) 9.11.2 Port 8 Functions The following table describes the mapping of the pins of Port 8 and the related I/O signals. Table 9-27 Port 8 Functions Port Pin Functionality Associated Port I/O Control Select.
Page 652 TC1784 General Purpose I/O Ports and Peripheral I/O Lines (Ports) Table 9-27 Port 8 Functions (cont’d) Port Pin Functionality Associated Port I/O Control Select. Reg./ I/O Line Reg./Bit Value Field P8.4 General-purpose input P8_IN.P4 P8_IOCR4. 0XXX General-purpose output P8_OUT.P4 1X00 Reserved –...
Page 653 TC1784 General Purpose I/O Ports and Peripheral I/O Lines (Ports) Table 9-27 Port 8 Functions (cont’d) Port Pin Functionality Associated Port I/O Control Select. Reg./ I/O Line Reg./Bit Value Field P8.8 General-purpose input P8_IN.P8 P8_IOCR8. 0XXX General-purpose output P8_OUT.P8 1X00 Reserved –...
Page 654 TC1784 General Purpose I/O Ports and Peripheral I/O Lines (Ports) Table 9-27 Port 8 Functions (cont’d) Port Pin Functionality Associated Port I/O Control Select. Reg./ I/O Line Reg./Bit Value Field P8.12 I General-purpose input P8_IN.P12 P8_IOCR12. 0XXX PC12 General-purpose output P8_OUT.P12...
Page 655: Port 8 Pad Driver Mode Register
TC1784 General Purpose I/O Ports and Peripheral I/O Lines (Ports) 9.11.2.1 Port 8 Pad Driver Mode Register P8_PDR Port 8 Pad Driver Mode Register Reset Value: 0000 0000 Field Bits Type Description [2:0] Pad Driver Mode for P8.[3:0] (Class A2 pads; coding see...
Page 656: Port 9
TC1784 General Purpose I/O Ports and Peripheral I/O Lines (Ports) 9.12 Port 9 Port 9 is an 8-bit GPIO port. 9.12.1 Port 9 Registers For this port, all pins can be read as GPIO, from the Port Input Register. Table 9-28...
Page 657: Port 9 Functions
TC1784 General Purpose I/O Ports and Peripheral I/O Lines (Ports) 9.12.2 Port 9 Functions Port 9 is an 8-bit port containing the third CAN node. The following table describes the mapping of the pins of Port 9 and the related I/O signals.
Page 658 TC1784 General Purpose I/O Ports and Peripheral I/O Lines (Ports) Table 9-29 Port 9 Functions (cont’d) Port I/O Pin Functionality Associated Reg./ Port I/O Control Select. I/O Line Reg./Bit Field Value P9.5 General-purpose input P9_IN.P3 P9_IOCR4.PC1 0XXX General-purpose output P9_OUT.P3...
Page 659: Port 9 Pad Driver Mode Register
TC1784 General Purpose I/O Ports and Peripheral I/O Lines (Ports) 9.12.2.1 Port 9 Pad Driver Mode Register P9_PDR Port 9 Pad Driver Mode Register Reset Value: 0000 0000 PDCAN Field Bits Type Description [2:0] Pad Driver Mode for P9.0,2,3 (Class A1 pads; coding see...
Page 660: Port 10
TC1784 General Purpose I/O Ports and Peripheral I/O Lines (Ports) 9.13 Port 10 Port 10 is a 14-bit GPIO port with EBU functionality. 9.13.1 Port 10 Registers For this port, all pins can be read as GPIO, from the Port Input Register.
Page 661: Port 10 Functions
TC1784 General Purpose I/O Ports and Peripheral I/O Lines (Ports) 9.13.2 Port 10 Functions Port 10 is a 14-bit port. The following table describes the mapping of the pins of Port 10 and the related I/O signals. Table 9-31 Port 10 Functions...
Page 662 TC1784 General Purpose I/O Ports and Peripheral I/O Lines (Ports) Table 9-31 Port 10 Functions (cont’d) Port Pin Functionality Associated Port I/O Control Select. Reg./ I/O Line Reg./Bit Value Field P10.3 General-purpose input P10_IN.P3 P10_IOCR0. 0XXX SSC2 input SLSI2B General-purpose output P10_OUT.P3...
Page 663 TC1784 General Purpose I/O Ports and Peripheral I/O Lines (Ports) Table 9-31 Port 10 Functions (cont’d) Port Pin Functionality Associated Port I/O Control Select. Reg./ I/O Line Reg./Bit Value Field P10.8 General-purpose input P10_IN.P8 P10_IOCR8. 0XXX General-purpose output P10_OUT.P8 1X00 Reserved –...
Page 664 TC1784 General Purpose I/O Ports and Peripheral I/O Lines (Ports) Table 9-31 Port 10 Functions (cont’d) Port Pin Functionality Associated Port I/O Control Select. Reg./ I/O Line Reg./Bit Value Field P10.13 I General-purpose input P10_IN.P13 P10_IOCR1 0XXX 2.PC13 General-purpose output P10_OUT.P13...
Page 665: Port 10 Pad Driver Mode Register
TC1784 General Purpose I/O Ports and Peripheral I/O Lines (Ports) 9.13.2.1 Port 10 Pad Driver Mode Register P10_PDR Port 10 Pad Driver Mode Register Reset Value: 0000 0000 Field Bits Type Description [2:0] Pad Driver Mode for P10.[3:0] (Class A1+ pads; coding see...
Page 666: Peripheral Control Processor (Pcp)
Peripheral Control Processor (PCP) This chapter describes the Peripheral Control Processor (PCP), its architecture, programming model, registers, and instructions. The TC1784’s PCP is an enhanced version of the TC1767’s and TC1797’s PCP peripheral control processor, which is an enhanced version of the TC1766’s and TC1796’s PCP, which is again an enhanced version of the TC1775 PCP.
Page 667: Switchable Core Clock Ratio
10.2 Peripheral Control Processor Overview The PCP in the TC1784 performs tasks that would normally be performed by the combination of a DMA controller and its supporting CPU interrupt service routines in a traditional computer system. It could easily be considered as the host processor’s first line of defence as an interrupt-handling engine.
Page 668: Pcp Architecture
TC1784 Peripheral Control Processor (PCP) 10.3 PCP Architecture The PCP is made up of several modular blocks as follows. Please refer to Figure • PCP Processor Core • Code Memory (CMEM) • Parameter Memory (PRAM) • PCP Interrupt Control Unit (PICU) •...
Page 669: Pcp Processor
TC1784 Peripheral Control Processor (PCP) 10.3.1 PCP Processor The PCP Processor is the main engine of the PCP. It contains an instruction pipeline, a set of GPRs, an arithmetic/logic unit (ALU), as well as control and status registers and logic. Its instruction set is optimized especially for the tasks it has to perform.
Page 670: Pcp Code Memory
Page 152 for the implemented type and size of the code memory in the TC1784. The PCP CMEM is viewed from the FPI Bus as a 32-bit wide memory, that must be accessed with 32-bit (word) accesses, and is addressed with byte addresses. Thus, care has to be taken when calculating PCP instruction FPI addresses.
Page 671: Pram Protection
TC1784 Peripheral Control Processor (PCP) concatenated with a 6-bit offset, is provided for arbitrary access to the PRAM. The effective address is a 14-bit word address, allowing a PRAM size of up to 64 Kbytes. The actual type (SRAM, DRAM, etc.) and size of the parameter RAM is implementation- specific;...
Page 672 TC1784 Peripheral Control Processor (PCP) program when it is suspended in favor of a higher-priority Service Request. Please refer Section 10.6.3 for more detailed information on the operation of these nodes. User´s Manual 10-7 V1.1, 2011-05 PCP, V2.09...
Page 673: Pcp Programming Model
TC1784 Peripheral Control Processor (PCP) 10.4 PCP Programming Model The PCP programming model can be viewed as a set of autonomous programs, or tasks, called channel programs, that share the processing resources of the PCP. Channel programs may be short and simple, or very complex; but they can coexist persistently within the PCP.
Page 674: Register R0
TC1784 Peripheral Control Processor (PCP) R7 is the only one of the eight registers that may not be used as a full GPR. The most significant 16 bits of R7 may not be written, and will always read back as 0. However, no error will occur when writing to the most significant 16 bits.
Page 675: Register R6
TC1784 Peripheral Control Processor (PCP) 10.4.1.4 Register R6 Register R6 may also be used as a general-use register. Again however, there are some instructions that use fields within R6. If the COPY or EXIT instructions are used, then the field R6.CNT1 can optionally be used implicitly as a counter. If an EXIT instruction is used that causes an interrupt, R6.SRPN and R6.TOS must be configured properly prior...
Page 676: Register R7
TC1784 Peripheral Control Processor (PCP) 10.4.1.5 Register R7 Register R7 is an exception with respect to the other registers in that not all bits within the register can be written, and the implicit use of the remaining bits virtually excludes the use of R7 as a GPR.
Page 677 TC1784 Peripheral Control Processor (PCP) PCP Register R7 Reset Value: 0000 0000 DPTR RES CEN IEN CNZ Field Bits Type Description [31:16] r Reserved read as 0; should be written with 0. DPTR [15:8] Data Pointer Segment Address for PRAM...
Page 678: Contexts And Context Models
TC1784 Peripheral Control Processor (PCP) 10.4.2 Contexts and Context Models After initialization, the instruction sequence of a PCP channel program is permanently stored (i.e. usually at least as long as the application is running) in the CMEM, and data parameters are held in the PRAM. These will remain stored regardless of whether a...
Page 679 TC1784 Peripheral Control Processor (PCP) To distinguish the actual register contents from the copies stored in the PRAM context regions, the term CRx is used throughout the rest of this document to refer to the register values in the context regions. Registers R6 and R7 are always handled in a special way...
Page 680 TC1784 Peripheral Control Processor (PCP) Stored Context in PRAM PCP Register Set Restore Full Context 8 Words Save Small Context Restore 4 Words Save Minimum Context Restore 2 Words Save MCA06136 Figure 17 PCP Context Models User´s Manual 10-15 V1.1, 2011-05...
Page 681: Context Save Area
PRAM in the TC1784. As an example, a PRAM of 2 Kbytes, solely used for the CSA, can store up to 255 Minimum Contexts, allowing the highest SRPN used for a PCP service request to be 255 (remember, an SRPN of 0 and an associated context region is never used;...
Page 682 TC1784 Peripheral Control Processor (PCP) If portions of the PRAM are used for other variables and global data, the space available for the CSA and the range of valid SRPNs is reduced by the memory space required for this data. For best utilization of PRAM, it is advisable to have the CSA grow upwards as a contiguous area without any “holes”, meaning that all SRPNs in the range 1 …...
Page 683 TC1784 Peripheral Control Processor (PCP) Full Context Small Context Minimum Context PRAM PRAM PRAM Memory Memory Memory Context SRPN = n1 n1×8 Context SRPN = n2 n2×4 Context SRPN = n3 Context n3×2 SRPN = 2 Context SRPN = 3...
Page 684: Context Restore Operation For Cr6 And Cr7
TC1784 Peripheral Control Processor (PCP) When choosing the Context Model for a given application, the following considerations can be helpful. When choosing the Small or the Minimum Context Models, save and restore operations for registers not handled in the automatic context operations can still be handled through explicit load and store instructions under control of the user.
Page 685 TC1784 Peripheral Control Processor (PCP) Channel Resume Mode Figure 19 illustrates the operation of a context restore for a “new” channel program when Channel Resume Mode has been selected (see Page 28). The PC is loaded from CR7[31:16], and the lower half of R7 is loaded from CR7[15:0]. The operating priority of the channel is taken from CR6[31:24] and all of R6 is loaded from CR6.
Page 686 TC1784 Peripheral Control Processor (PCP) Channel Restart Mode Figure 20 illustrates the operation of a context restore for a “new” channel program when Channel Restart Mode has been selected (see Page 27). The PC is loaded with the channel entry table address, and the lower half of R7 is loaded from CR7[15:0]. The upper half of CR6 is discarded.
Page 687 TC1784 Peripheral Control Processor (PCP) Suspended Channel Restart Figure 21 illustrates the operation of a context restore for a “suspended” channel program. The PC is loaded from CR7[31:16] (regardless of the Channel Start Mode), and the lower half of R7 is loaded from CR7[15:0]. All of R6 is loaded from CR6. The figure also shows how the operating priority of the channel (PCP_IR.CPPN) is restored from...
Page 688: Context Save Operation For Cr6 And Cr7
TC1784 Peripheral Control Processor (PCP) 10.4.2.4 Context Save Operation for CR6 and CR7 The operation of R6 and R7 context save varies according to whether the save operation is the result of a channel exit condition, or whether the channel is being suspended in favor of a higher-priority channel program.
Page 689 TC1784 Peripheral Control Processor (PCP) Channel Restart Mode Figure 23 illustrates the operation of a context save for a channel exit when Channel Restart Mode has been selected. This is the same as for Channel Resume mode except that the PC value is discarded, and the appropriate Channel Entry Table address is written to CR7[31:16].
Page 690 TC1784 Peripheral Control Processor (PCP) Channel Suspend Figure 24 illustrates the operation of a context save for a channel that is being suspended. This is the same as for Channel Resume mode except that an interrupt request is created to allow the channel to be restarted at a later time. This restore...
Page 691: Initialization Of The Contexts
TC1784 Peripheral Control Processor (PCP) 10.4.2.5 Initialization of the Contexts The programmer is responsible for configuring each channel program’s context before commencing operation. Because this must be done by writing to the PCP across the FPI Bus, it is important to understand exactly where each channel program’s context is from...
Page 692: Channel Programs
PCP channels. The individual channel programs for the individual PCP service requests can usually be viewed as independent and separate programs. There is no background program defined and running for the PCP in TC1784 as there would be with traditional processors.
Page 693: Channel Resume Mode
TC1784 Peripheral Control Processor (PCP) It is recommended that all EXIT instructions for all channels should use the EP = 0 setting when the PCP is operated in Channel Restart Mode (see Page 110). Note that when Channel Restart Mode is in use a Channel Entry Table must be provided with a valid entry for every channel being used.
Page 694 TC1784 Peripheral Control Processor (PCP) Channel Restart Mode Channel Resume Mode Code Memory Code Memory CMEM CMEM Channel #2 Main Code Channel #n1 Main Code Channel #2 Main Code Channel #3 Main Code Channel #n1 Channel #1 Main Code Main Code...
Page 695: Pcp Operation
10.5.1 PCP Initialization The PCP is placed in a quiescent state when the TC1784 is first powered-on or reset. Before a channel program can be enabled, the PCP as a whole must be initialized by some other FPI Bus master, typically the CPU. Initialization steps include: •...
Page 696: Channel Exit And Context Save Operation
TC1784 Peripheral Control Processor (PCP) After the channel program starts, the value of R6 may be changed without altering the value of the effective CPPN, because updates to the value of R6.CPPN have no effect until the next invocation of the channel program.
Page 697: Error Condition Channel Exit
TC1784 Peripheral Control Processor (PCP) • If ST = 1 is specified bit R7.CEN (Channel Enable) is cleared (i.e. the channel is disabled). • If EP = 0 is specified or PCP_CS.RCB = 1 (Channel Restart Mode has been selected), the PCP program counter to be saved to context location CR7.PC is set to the appropriate channel entry table address.
Page 698: Debug Exit
TC1784 Peripheral Control Processor (PCP) • The PC of the instruction that was executing when the error occurred is stored in PCP_ES.EPC. • The number of the channel program that was executing when the error occurred is stored in PCP_ES.EPN.
Page 699: Pcp Interrupt Operation
TC1784 Peripheral Control Processor (PCP) Note: The DEBUG instruction must be only used in DEBUG mode; otherwise an “Illegal Operation” (IOP) error will be generated. 10.6 PCP Interrupt Operation The PICU and the PSRNs (PCP_SRC[11:0]) are similar to the CPU’s ICU and all other SRNs in the system.
Page 700: Issuing Service Requests To Cpu Or Pcp
TC1784 Peripheral Control Processor (PCP) 10.6.1 Issuing Service Requests to CPU or PCP The PCP may use one of two mechanisms to raise an interrupt request to the CPU or itself. The first, and most inefficient, method for a PCP channel program is to issue service requests by performing an FPI Bus write operation to an external service request node (SRN).
Page 701: Issuing Pcp Service Requests
(x = 4 to 8) with a TOS value representing a non-available interrupt bus or 11 in the TC1784) will disable Service Request Node x. The actual service request flag and the service request priority number of the PCP_SRCx registers are updated by the PCP when it generates an implicit service request.
Page 702: Service Request On Exit Instruction
TC1784 Peripheral Control Processor (PCP) Further differences between these three mechanisms are detailed in the following sections. 10.6.4.1 Service Request on EXIT Instruction An implicit PCP service request is issued when the INT field of the EXIT instruction is set to 1 and the specified condition code, cc_B, of this instruction is true.
Page 703: Service Request On Error
TC1784 Peripheral Control Processor (PCP) Extended Service Request Node. This allows for the posting of an interrupt request to the PCP on exit from the new channel program. 10.6.4.3 Service Request on Error While a service request triggered through an EXIT instruction is optional and can be issued either to the CPU or to the PCP itself, a service request due to an error condition will always be automatically issued and will always be directed to the CPU.
Page 704: Pram Protection
TC1784 Peripheral Control Processor (PCP) To avoid such a deadlock, the PICU performs a special arbitration round as soon as the PCP queue becomes full. In this arbitration round, only the service request nodes assigned to the PCP queue are allowed to participate; all service requests from nodes external to the PCP are excluded, regardless of whether their priorities are higher or lower than those of the PCP queue.
Page 705 TC1784 Peripheral Control Processor (PCP) Writable by FPI? Region Writable by PCP Software? Open PRAM PPROT.FBASE General Channel PRAM PPROT.PSIZE Yes/No Protected Channel PRAM (can be limited to writes by Protected Channels only) CS.PPS Yes/No Context (can be protected against...
Page 706: Protection Of Pram Against Fpi Writes
TC1784 Peripheral Control Processor (PCP) write access to an area of PRAM that cannot be modified by an Unprotected Channel Program. Determination of whether a channel is Protected or Unprotected is performed by examination of the channel number against a programmable threshold (programmed via PCP_PPROT.PTHRES).
Page 707: Protected Channel Pram Protection
TC1784 Peripheral Control Processor (PCP) Note: This scheme also limits the number of Channel Programs that can be invoked. Note: FPI PRAM write accesses to PRAM are unaffected by this protection. 10.7.2.2 Protected Channel PRAM Protection To ensure that an Unprotected Channel Program cannot corrupt the PRAM assigned to a protected channel program it is necessary to protect the PRAM space used by the protected channels from instruction executed by non-protected channels.
Page 708: Operation As An Fpi Slave
TC1784 Peripheral Control Processor (PCP) This function is controlled by the PCP_FWWIN register (see Page 86). 10.8.2 Operation as an FPI Slave The PCP is visible to FPI Masters as a 256 Kbyte R/W block of memory on the System Bus.
Page 709: Pcp Error Handling
TC1784 Peripheral Control Processor (PCP) 10.9 PCP Error Handling The PCP contains a number of fail-safe mechanisms to ensure that error conditions are handled gracefully and predictably. In addition to providing an extra level of system robustness suitable for high integrity and safety-critical systems, these mechanisms can often ease the task of finding programming errors during the development process.
Page 710: Protected Channel Pram
TC1784 Peripheral Control Processor (PCP) • An incoming interrupt request causes the PCP to attempt to load a context from outside the CSA. This prevents the PCP from running an invalid channel program as a result of an invalid interrupt request.
Page 711: Instruction Address Error
TC1784 Peripheral Control Processor (PCP) Note: The DEBUG instruction must be only used in DEBUG mode otherwise it will be considered to be an illegal operation and will generate an IOP error. 10.9.5 Instruction Address Error An Instruction Address Error is generated if the PCP attempts to execute an instruction from an illegal address.
Page 712: Memory Integrity Error Detection
TC1784 Peripheral Control Processor (PCP) Data Array Mapping, no error detection No mapping of the bits is performed. Writes to the memory will not affect the bits. Error detection for the memory is disabled. Normal operation (with the exception that protection is not operational) is possible.
Page 713: Instruction Set Overview
10.12 Instruction Set Overview The following sections present an overview of the instruction set and the available addressing modes of the PCP in the TC1784. 10.12.1 DMA Primitives Table 18 describes the two DMA instructions of the PCP.
Page 714: Load And Store
TC1784 Peripheral Control Processor (PCP) 10.12.2 Load and Store Table 19 describes the load and store instructions of the PCP. Note: If a conditional instruction’s condition code is false, the operation will be treated as a “No Operation”. Register values will not be changed and the flags will not be updated.
Page 715: Arithmetic And Logical Instructions
TC1784 Peripheral Control Processor (PCP) 10.12.3 Arithmetic and Logical Instructions Arithmetic instructions that are fully register-based execute conditionally depending on the specified Condition Code A (see Page 94). All other arithmetic instructions such as PRAM (.PI), indirect (.I), and FPI (.F and .IF) execute unconditionally.
Page 716 TC1784 Peripheral Control Processor (PCP) Table 27 Logical Instructions (cont’d) Logical Or Register OR register (conditionally) OR.F Content of FPI Bus address location OR register (byte, half-word or word) OR.PI Content of PRAM address location OR register MSET.PI Set specified bits within a PRAM location...
Page 717: Bit Manipulation
Set carry flag depending on value of specified register bit 10.12.5 Flow Control Table 23 describes flow control instructions of the PCP in the TC1784. Table 29 Flow Control Instructions Jump Jump conditionally to PC + short immediate offset address JC.A...
Page 718: Addressing Modes
TC1784 Peripheral Control Processor (PCP) 10.12.6 Addressing Modes The PCP needs to address locations in memory in different ways, as determined by the type of memory being accessed and the type of action being performed on that location. 10.12.6.1 FPI Bus Addressing All FPI Bus accesses from the PCP are indirect to some extent.
Page 719: Pram Addressing
TC1784 Peripheral Control Processor (PCP) 10.12.6.2 PRAM Addressing The PRAM is always addressed indirectly by the PCP. The normal address used is the value of the R7.DPTR field (8 bits) concatenated with an immediate 6-bit offset value encoded in the instruction, yielding a 14-bit word address. This enables access to 16 Kwords (64 Kbytes).
Page 720 TC1784 Peripheral Control Processor (PCP) • Effective JUMP Address[15:0] = NextPC + Sign-Extend(#offset6); +/- 32 instructions The function NextPC indicates the instruction that would be fetched next by the program counter. Instructions using this addressing are JL, JC and JC.I.
Page 721: Fpi Interface
10.13 FPI Interface Any FPI Bus master (on the TC1784’s System Peripheral Bus) can access the three distinct PCP address ranges from the FPI Bus side, on the other hand the PCP master interface can also access any address on the FPI bus. Normally, the CPU initializes the control registers via FPI Bus access.
Page 722: Access To The Pram From The Fpi Bus
TC1784 Peripheral Control Processor (PCP) This function is controlled by the RPROT register (“Register Protection Register, PCP_RPROT” on Page 80). 10.13.2 Access to the PRAM from the FPI Bus FPI Bus accesses to the PRAM must always be performed with word accesses; byte or half-word accesses will result in a bus error.
Page 723 TC1784 Peripheral Control Processor (PCP) The FPI Bus address of an instruction pointed to by the PCP program counter, PC, is calculated by the following formula: • Effective FPI Bus address[31:0] = (CMEM Base Address) + <PC> << 1 User´s Manual 10-58 V1.1, 2011-05...
Page 724: Debugging The Pcp
TC1784 Peripheral Control Processor (PCP) 10.14 Debugging the PCP For debugging the PCP, a special instruction, DEBUG, is provided. This instruction can only be used when the PCP is in Debug Mode. It can be placed at important locations inside the code to track and trace program execution. The execution of the instruction depends on a condition code specified with the instruction.
Page 725 TC1784 Peripheral Control Processor (PCP) changed by the operation of another active channel. In this case, the required registers should be explicitly saved to PRAM by store instructions prior to execution of the DEBUG instruction. If the DEBUG instruction is programmed to stop all channel program execution, the PCP disables further invocations of any channel by clearing bit PCP_CS.EN.
Page 726: Pcp Registers
TC1784 Peripheral Control Processor (PCP) 10.15 PCP Registers The PCP can be viewed as being a peripheral on the FPI Bus. As with any other peripheral, there are control registers, normally set by the CPU acting as an external FPI Bus master to the PCP during initialization.
Page 727 TC1784 Peripheral Control Processor (PCP) Control Registers Interrupt Registers PCP_CLC PCP_SRC0 PCP_CS PCP_SRC1 PCP_ES PCP_SRC2 PCP_ICR PCP_SRC3 PCP_ITR PCP_SRC4 PCP_ICON PCP_SRC5 PCP_SSR PCP_SRC6 PCP_RPROT PCP_SRC7 PCP_CPROT PCP_SRC8 PCP_PPROT PCP_SRC9 PCP_FWWIN PCP_SRC10 PCP_SMACON PCP_SRC11 PCP_MIECON PCP_MIESTATP PCP_MIESTATC MCA06150 Figure 28 PCP Registers...
Page 728 TC1784 Peripheral Control Processor (PCP) Table 31 Register Overview of PCP Short Name Description Offset Access Mode Reset Description Addr. Read Write PCP_CLC Clock Control U, SV, Page 65 Register 32, E Reset PCP_ID Module Identification U, SV, Page 66...
Page 729: Pcp Registers Address Space
TC1784 Peripheral Control Processor (PCP) Table 31 Register Overview of PCP (cont’d) Short Name Description Offset Access Mode Reset Description Addr. Read Write PCP_SRC9 Service Request U, SV, Page 91 Control Register 9 Reset PCP_SRC8 Service Request U, SV, Page 90...
Page 730: Registers
TC1784 Peripheral Control Processor (PCP) 10.17 Registers 10.17.1 PCP Clock Control Register, PCP_CLC PCP_CLC PCP Clock Control Register Reset Value: 0000 0000 Field Bits Type Description [31:16] r Reserved Read as 0; should be written with 0. PCGDIS Clock Gating Disable Bit Allows clock gating to be disabled.
Page 731: Pcp Module Identification Register, Pcp_Id
TC1784 Peripheral Control Processor (PCP) 10.17.2 PCP Module Identification Register, PCP_ID PCP_ID PCP Module Identification Register Reset Value: 0020 C0XX MODNUM ID32BIT REVNUM Field Bits Type Description MODNUM [31:16] r PCP Identification Number value = 0020 ID32BIT [15:8] 32-bit Module Identification Number Marker...
Page 732: Pcp Control And Status Register, Pcp_Cs
TC1784 Peripheral Control Processor (PCP) 10.17.3 PCP Control and Status Register, PCP_CS This register can be Endinit-protected via bit EIE. PCP_CS PCP Control/Status Register Reset Value: 0000 0000 EIE RCB RES RS RES EN Field Bits Type Description [31:24] rw Error Service Request Number SRPN for interrupt to CPU on an error condition.
Page 733 TC1784 Peripheral Control Processor (PCP) Field Bits Type Description [15:9] PRAM Partition Size Default, only allowed with PPE = 0 CSA contains 3 context save regions CSA contains 1 + 2 × 127 context save regions Note: The actual size of the CSA (in words) is given by ×...
Page 734: Pcp Error/Debug Status Register, Pcp_Es
TC1784 Peripheral Control Processor (PCP) Field Bits Type Description Channel Start Mode Control Channel resume operation mode selected; channel start PC is taken from restored context Channel restart operation mode selected; channel start PC is derived from the requested channel number (= priority number of service...
Page 735 Memory Error This bit is set if a PCP internal memory error has occurred. See Table 10.22 “Implementation of the PCP in the TC1784” on Page 152 for TC1784 specific implementation. Debug Event Flag Set if the last error/debug event was a debug event.
Page 736: Pcp Interrupt Control Register, Pcp_Icr
TC1784 Peripheral Control Processor (PCP) Field Bits Type Description Disabled Channel Request Flag Set if the last error/debug event was an error generated by receipt of an interrupt request with an SRPN that attempted to start a disabled PCP channel;...
Page 737 TC1784 Peripheral Control Processor (PCP) PCP_ICR PCP Interrupt Control Register Reset Value: 0000 0000 PARBCYC PIPN CPPN Field Bits Type Description [31:27] r Reserved Read as 0; should be written with 0. PONECYC Clocks per Arbitration Cycle Control This bit determines the number of clocks per arbitration cycle.
Page 738 TC1784 Peripheral Control Processor (PCP) Field Bits Type Description Reserved CPPN [7:0] Current PCP Priority Number This field indicates the current priority level of the PCP and is automatically updated by hardware on entry into an interrupt service routine. User´s Manual 10-73 V1.1, 2011-05...
Page 739: Pcp Interrupt Threshold Register, Pcp_Itr
TC1784 Peripheral Control Processor (PCP) 10.17.6 PCP Interrupt Threshold Register, PCP_ITR PCP_ITR PCP Interrupt Threshold Control Register Reset Value: 0000 0000 Field Bits Type Description [31:20] r Reserved Read as 0; should be written with 0. [19:16] rw Interrupt Threshold Level...
Page 740: Pcp Interrupt Configuration Register, Pcp_Icon
Interrupt bus 0 is always enabled. [7:6] PCP Interrupt Bus 3 TOS Mapping This field reflects the TOS associated with interrupt bus 3. Note: Interrupt bus 3 is not available in the TC1784. User´s Manual 10-75 V1.1, 2011-05 PCP, V2.09...
Page 741 PCP Interrupt Bus 2 TOS Mapping This field reflects the TOS associated with interrupt bus 2. Note: Interrupt bus 2 is not available in the TC1784. [3:2] PCP Interrupt Bus 1 TOS Mapping This field reflects the TOS associated with interrupt bus 1 (PCP interrupt arbitration bus).
Page 742: Pcp Stall Status Register, Pcp_Ssr
TC1784 Peripheral Control Processor (PCP) 10.17.8 PCP Stall Status Register, PCP_SSR PCP_SSR PCP Stall Status Register Reset Value: 0000 0000 SCHN STOS SSRN Field Bits Type Description [31:24] Reserved Read as 0. SCHN [23:16] PCP Stalled Channel Number This field shows the channel number of the channel that was executing when the last (or present) stall condition occurred.
Page 743 TC1784 Peripheral Control Processor (PCP) Field Bits Type Description SSRN [7:0] PCP Stalled Service Request Number This field shows the Service Request Number that was being posted when the last (or present) stall condition occurred. This field can only be cleared by a reset.
Page 744: Sist Mode Access Control Register, Pcp_Smacon
TC1784 Peripheral Control Processor (PCP) 10.17.9 SIST Mode Access Control Register, PCP_SMACON Note: Please see Section 10.10 Page 46 for more information regarding the use of this register. This register is ENDINIT protected. PCP_SMACON SIST Mode Access Control Register Reset Value: 0000 0000...
Page 745: Register Protection Register, Pcp_Rprot
TC1784 Peripheral Control Processor (PCP) 10.17.10 Register Protection Register, PCP_RPROT This register is ENDINIT protected. PCP_RPROT Register Protection Register Reset Value: 0000 0000 Field Bits Type Description Register Protection Enable Registers are not protected and can be written at any time.
Page 746: Cmem Protection Register, Pcp_Cprot
TC1784 Peripheral Control Processor (PCP) 10.17.11 CMEM Protection Register, PCP_CPROT Note: Please see Section 10.13.3 Page 57 for more information regarding the use of this register. This register is ENDINIT protected. PCP_CPROT CMEM Protection Register Reset Value: 0000 0000 Field...
Page 747: Pram Protection Register, Pcp_Pprot
TC1784 Peripheral Control Processor (PCP) 10.17.12 PRAM Protection Register, PCP_PPROT This register is ENDINIT protected. PCP_PPROT PRAM Protection Register Reset Value: 0000 0000 PTHRES PSIZE FBASE Field Bits Type Description PRAM Protection Enable for FPI Writes PRAM is not protected and can be written via FPI at any time.
Page 748 TC1784 Peripheral Control Processor (PCP) Field Bits Type Description PRAM Protection Enable for Internal Writes The entire PRAM (subject to PRAM partitioning) is not protected and can be written using PCP PRAM write instructions. All PRAM outside the Protected Window (and...
Page 749 TC1784 Peripheral Control Processor (PCP) Field Bits Type Description PTHRES [23:16] Protected Channel Threshold When PPROT.ENI is ‘0’, this field has no effect. When PPROT.ENI is ‘1’, this field defines the Channel number which is used to distinguish between protected and non-protected Channels.
Page 750 TC1784 Peripheral Control Processor (PCP) Field Bits Type Description FBASE [7:0] PRAM FPI Open Window Base When PPROT.EN is ‘0’, this field has no effect. When PPROT.EN is '1' (see above) this field defines the base address (in multiples of 256 bytes and relative to the base of PRAM) of the region at the top of PRAM that remains writable by FPI writes.
Page 751: Fpi Write Window Register, Pcp_Fwwin
TC1784 Peripheral Control Processor (PCP) 10.17.13 FPI Write Window Register, PCP_FWWIN Note: Please see Section 10.8.1 Page 42 for more information regarding the use of this register. This register is ENDINIT protected. PCP_FWWIN FPI Write Window Register Reset Value: 0000 0000...
Page 752: Pcp Service Request Control Registers M, Pcp_Src[1:0]
TC1784 Peripheral Control Processor (PCP) Field Bits Type Description SIZE [28:24] Window Size The FPI window size (binary sizing) 256 bytes 512 bytes (n+8) bytes BASE [23:0] Window Base Address Controls the base address of the FPI window, binary aligned according to the window size.
Page 753 TC1784 Peripheral Control Processor (PCP) Field Bits Type Description PCP Node m Service Request Flag No service requested (default). Valid active service requested. PCP Node m Service Request Enable Always read as 1 (enabled). [11:10] PCP Node m Type-of-Service State Always read as 00 .
Page 754: Pcp Service Request Control Registers M, Pcp_Src[3:2]
TC1784 Peripheral Control Processor (PCP) 10.17.15 PCP Service Request Control Registers m, PCP_SRC[3:2] Service request nodes for interrupt bus 1 (PCP interrupt arbitration bus). PCP_SRCm (m = 2-3) PCP Service Request Control Register m -m*4 Reset Value: 0000 1400 SRPN...
Page 755: Pcp Service Request Control Registers M, Pcp_Src[8:4]
TC1784 Peripheral Control Processor (PCP) 10.17.16 PCP Service Request Control Registers m, PCP_SRC[8:4] Service request nodes programmable for interrupt bus 0 (CPU interrupt arbitration bus) or 1 (PCP interrupt arbitration bus). PCP_SRCm (m = 4-8) PCP Service Request Control Register m...
Page 756: Pcp Service Request Control Registers M, Pcp_Src[11:9]
TC1784 Peripheral Control Processor (PCP) Field Bits Type Description SRPN [7:0] PCP Node m Service Request Priority Number This number is automatically set by the PCP if it needs to place a service request on interrupt bus 0 (CPU interrupt arbitration bus) or 1 (PCP interrupt arbitration bus).
Page 757 TC1784 Peripheral Control Processor (PCP) Field Bits Type Description SRCN [23:16] PCP Node m Service Request Channel Number Channel Number Entry (default = 0). When the PCP interrupt request was raised by the PCP Processor Core when executing an EXIT instruction, then this bit field contains the SRPN value taken from R6 when the exit instruction was executed.
Page 758: Pcp Instruction Set Details
TC1784 Peripheral Control Processor (PCP) 10.18 PCP Instruction Set Details This section describes the instruction set architecture of the PCP in detail. 10.18.1 Instruction Codes and Fields All PCP instructions use a common set of fields to describe such things as the source register, and the state of flags.
Page 759: Conditional Codes
TC1784 Peripheral Control Processor (PCP) 10.18.1.1 Conditional Codes Many PCP instructions have the option of being executed conditionally. The condition code of an instruction is the field that specifies the condition to be tested before the instruction is executed. Depending on the type of instruction there are 8 or 16 condition codes available.
Page 760: Instruction Fields
TC1784 Peripheral Control Processor (PCP) 10.18.1.2 Instruction Fields Table 34 lists the instruction field definitions of the PCP instruction set architecture. Note: The exact syntax for these fields may be different depending on which tool (e.g. assembler) is used. Please refer to the respective tool descriptions.
Page 761 TC1784 Peripheral Control Processor (PCP) Table 34 Instruction Field Definitions (cont’d) Symbol Syntax Description Stop PCP DAC = 0 Allow the PCP to continue to execute channel programs in response to service requests. DAC = 1 Prevent the PCP from executing further channel programs (PCP_CS.EN = 0).
Page 762 TC1784 Peripheral Control Processor (PCP) Table 34 Instruction Field Definitions (cont’d) Symbol Syntax Description SIZE Data Size Control SIZE = 00 Byte (8-bit) SIZE = 01 Half-word (16-bit) SIZE = 10 Word (32-bit) SIZE = 11 Reserved SRC+- Source Address Pointer Control...
Page 763: Counter Operation For Copy Instruction
TC1784 Peripheral Control Processor (PCP) 10.18.2 Counter Operation for COPY Instruction Figure 10 - 1 shows the flow of a COPY instruction. COPY Instruction t_count := CNT0 DATA Transfer t_count := t_count - 1 t_count = 0 ? CNC = ?
Page 764: Counter Operation For Bcopy Instruction
TC1784 Peripheral Control Processor (PCP) 10.18.3 Counter Operation for BCOPY Instruction Figure 10 - 2 shows the flow of a BCOPY instruction. BCOPY Instruction DATA Transfer (Block size determined by CNT0 field) CNC = ? CNT1 := CNT1 - 1...
Page 765: Divide And Multiply Instructions
TC1784 Peripheral Control Processor (PCP) 10.18.4 Divide and Multiply Instructions The PCP has Multiply and Divide capabilities (unsigned values only). All Multiply and divide instructions operate on 8 bits of data (taken from the dividend for divide, from the multiplicand for multiply). This strategy allows the user to implement the appropriate number of instructions (“steps”) as required for the user’s data format.
Page 766: Add, 32-Bit Addition
TC1784 Peripheral Control Processor (PCP) a 40-bit unsigned multiply and then shifts this result right by 8 bits (discards the least significant 8 bits of the 40-bit result). The DSTEP instruction also has some conditions stipulated regarding input values to the instruction.
Page 767: And, 32-Bit Logical And
TC1784 Peripheral Control Processor (PCP) 10.18.6 AND, 32-bit Logical AND This section describes the AND instructions of the PCP. Syntax AND Rb, Ra, cc_A Description If the condition CONDCA is true, then perform a bit-wise logical AND of the contents of register Ra and the contents of register Rb;...
Page 768: Bcopy, Dma Operation
TC1784 Peripheral Control Processor (PCP) 10.18.7 BCOPY, DMA Operation This section describes the BCOPY instruction of the PCP in the TC1784. BCOPY Syntax BCOPY DST+-, SRC+-, CNC, CNT0 Description Allows the PCP to perform DMA type transfers using FPI block transfers.
Page 769: Chkb, Check Bit
TC1784 Peripheral Control Processor (PCP) 10.18.8 CHKB, Check Bit This section describes the CHKB instruction of the PCP. CHKB Syntax CHKB Ra, #imm5, S/C Description If bit imm5 of register Ra is equal to the specified test value S/C then set the carry flag R7.C, else clear the carry flag.
Page 770: Comp, 32-Bit Compare
TC1784 Peripheral Control Processor (PCP) 10.18.10 COMP, 32-bit Compare This section describes the COMP instructions of the PCP. COMP Syntax COMP Rb, Ra, cc_A Description If the condition CONDCA is true, then subtract the contents of register Ra from the contents of register Rb; set the flags in register R7 according to the result of the subtraction;...
Page 771: Copy, Dma Instruction
TC1784 Peripheral Control Processor (PCP) 10.18.11 COPY, DMA Instruction This section describes the COMP instruction of the PCP. COPY Syntax COPY DST+-, SRC+-, CNC, CNT0, SIZE Description Moves the contents of FPI Bus source location to FPI Bus destination location. Source location is pointed to by the contents of register R4;...
Page 772: Debug, Debug Instruction
TC1784 Peripheral Control Processor (PCP) 10.18.12 DEBUG, Debug Instruction This section describes the DEBUG instruction of the PCP. DEBUG Syntax DEBUG EDA, DAC, RTA, SDB, cc_B Description Conditionally cause a debug event if condition CONDCB is true. Optionally stop channel execution (SDB = 1) and/or generate an external debug event (EDA = 1).
Page 773: Dinit, Divide Initialization
TC1784 Peripheral Control Processor (PCP) 10.18.13 DINIT, Divide Initialization This section describes the DINIT instruction of the PCP. DINIT Syntax DINIT <R0>, Rb, Ra Description Initialize Divide logic ready for divide sequence (Rb / Ra) and Clear R0. If value of Ra is 0 then set V (to flag divide by 0 error);...
Page 774: Dstep, Divide Instruction
TC1784 Peripheral Control Processor (PCP) 10.18.14 DSTEP, Divide Instruction This section describes the DSTEP instruction of the PCP. DSTEP Syntax DSTEP <R0>, Rb, Ra Description Perform 1 step (eight bits) of an unsigned 32- by 32-bit divide (Rb / Ra). Shift R0 left by 8 bits, copy the most significant byte of Rb into LS byte of R0.
Page 775: Exit, Exit Instruction
TC1784 Peripheral Control Processor (PCP) 10.18.15 EXIT, Exit Instruction This section describes the EXIT instruction of the PCP. EXIT Syntax EXIT EC, ST, INT, EP, cc_B Description Unconditionally exit channel program execution. Optionally decrement counter CNT1 (EC = 1), disable further channel invocation (ST = 1), generate an interrupt request (INT = 1) if condition CONDCB is true.
Page 776: Inb, Insert Bit
TC1784 Peripheral Control Processor (PCP) 10.18.16 INB, Insert Bit This section describes the INB instructions of the PCP. Syntax INB Rb, Ra, cc_A Description If CONDCA is true, then insert the carry flag R7.C into register Rb at the bit position specified through bits [4..0] of register Ra.
Page 777: Jc, Jump Conditionally
TC1784 Peripheral Control Processor (PCP) 10.18.17 JC, Jump Conditionally This section describes the conditional jump instructions of the PCP. Syntax JC offset6, cc_B Description If CONDCB is true, then add the sign-extended value specified by offset6 to the contents of the PC, and jump to that address.
Page 778: Jl, Jump Long Unconditional
TC1784 Peripheral Control Processor (PCP) 10.18.18 JL, Jump Long Unconditional This section describes the long jump instruction JL of the PCP. Syntax JL offset10 Description Add the sign-extended value specified by offset10 to the contents of the PC, and jump to that address.
Page 779 TC1784 Peripheral Control Processor (PCP) LD.P Syntax LD.P Rb, [Ra], cc_A Description If condition CONDCA is true, then load the contents of the PRAM address location, specified by the addition of contents of the PRAM Data Pointer, shifted left by six bits, and the zero-extended 6-bit value Ra[5:0] into register Rb.
Page 780: Ldl, Load 16-Bit Value
TC1784 Peripheral Control Processor (PCP) 10.18.20 LDL, Load 16-bit Value This section describes the LDL instructions of the PCP. LDL.IL Syntax LDL.IL Ra, #imm16 Description Load the immediate value imm16 into the lower bits of register Ra (bits [15:0]). Bits [31:16] of register Ra are unaffected.
Page 781: Mov, Move Register To Register
TC1784 Peripheral Control Processor (PCP) 10.18.22 MOV, Move Register to Register This section describes the MOV instruction of the PCP. Syntax MOV Rb, Ra, cc_A Description If condition CONDCA is true, then move the contents of register Ra into register Rb. If CONDCA is false, no operation is performed.
Page 782: Multiply Instructions
TC1784 Peripheral Control Processor (PCP) 10.18.23 Multiply Instructions This section describes the multiply instructions of the PCP. MSTEP32 Syntax MSTEP32 <R0>, Rb, Ra Description Perform an unsigned multiply step, using eight bits of data taken from Rb, keeping the least significant 32 bits of a potential 64-bit result.
Page 783: Neg, Negate
TC1784 Peripheral Control Processor (PCP) 10.18.24 NEG, Negate This section describes the NEG instruction of the PCP. Syntax NEG Rb, Ra, cc_A Description If condition CONDCA is true, then move the 2’s complement of the contents of register Ra into register Rb. If CONDCA is false, no operation is performed.
Page 784: Or, Logical Or
TC1784 Peripheral Control Processor (PCP) 10.18.27 OR, Logical OR This section describes the OR instructions of the PCP. Syntax OR Rb, Ra, cc_A Description If the condition CONDCA is true, then perform a bit-wise logical OR of the contents of register Ra and the contents of register Rb;...
Page 785: Pram Bit Operations
TC1784 Peripheral Control Processor (PCP) 10.18.28 PRAM Bit Operations This section describes the MCLR and MSET instructions of the PCP. MCLR Syntax MCLR.PI Ra, [#offset6] Description Perform an ‘AND’ of the contents of the specified register with the contents of the PRAM location specified by the addition of contents of the PRAM Data Pointer, shifted left by six bits, and the zero-extended 6-bit value offset.
Page 786: Pri, Prioritize
TC1784 Peripheral Control Processor (PCP) 10.18.29 PRI, Prioritize This section describes the PRI instruction of the PCP. PRId Syntax PRI Rb, Ra, cc_A Description If condition CONDCA is true, then find the bit position of the most significant 1 in register Ra and put the number into register Rb.
Page 787: Rl, Rotate Left
TC1784 Peripheral Control Processor (PCP) 10.18.30 RL, Rotate Left This section describes the RL instruction of the PCP. Syntax RL Ra, #imm5 Description Rotate the contents of register Ra to the left by the number of bit positions specified through the 5-bit value imm5. The values defined for imm5 are 1, 2, 4 and 8.
Page 788: Set, Set Bit
TC1784 Peripheral Control Processor (PCP) 10.18.32 SET, Set Bit This section describes the SET bit instruction of the PCP. Syntax SET Ra, #imm5 Description Set bit imm5 of register Ra to 1. Operation R[a][imm5] = 1 Flags None SET.F Syntax SET.F [Ra], #imm5, Size...
Page 789: Shr, Shift Right
TC1784 Peripheral Control Processor (PCP) 10.18.34 SHR, Shift Right This section describes the SHR instruction of the PCP. Syntax SHR Ra, #imm5 Description Shift the contents of register Ra to the right by the number of bit positions specified through the 5-bit value imm5. The values allowed for imm5 are 1, 2, 4 and 8.
Page 790: St, Store
TC1784 Peripheral Control Processor (PCP) 10.18.35 ST, Store This section describes the ST instructions of the PCP. ST.F Syntax ST.F Rb, [Ra], Size Description Store the contents of register Rb to the address location specified by the contents of register Ra. When the Size is byte or half-word, the data is stored with the internal LSB (bit 0) properly aligned to the correct FPI Bus byte or half-word lane.
Page 791: Sub, 32-Bit Subtract
TC1784 Peripheral Control Processor (PCP) 10.18.36 SUB, 32-bit Subtract This section describes the SUB instructions of the PCP. Syntax SUB Rb, Ra, cc_A Description If the condition CONDCA is true, then subtract the contents of register Ra from the contents of register Rb; place the result in Rb.
Page 792: Xch, Exchange
TC1784 Peripheral Control Processor (PCP) 10.18.37 XCH, Exchange This section describes the XCH instructions of the PCP. XCH.F Syntax XCH.F Rb, [Ra], Size Description Exchange contents of R[b] and FPI[R[a]] when Size is byte or half-word, the value is stored with the internal LSB (bit 0) properly aligned to the correct FPI byte or half-word lane.
Page 793: Xor, 32-Bit Logical Exclusive Or
TC1784 Peripheral Control Processor (PCP) 10.18.38 XOR, 32-bit Logical Exclusive OR This section describes the XOR instructions of the PCP. Syntax XOR Rb, Ra, cc_A Description If the condition CONDCA is true, then perform a bit-wise logical Exclusive-OR of the contents of register Ra and the contents of register Rb;...
Page 794: Flag Updates Of Instructions
TC1784 Peripheral Control Processor (PCP) 10.18.39 Flag Updates of Instructions Most instructions update the state flags in R7. In Table 35, each instruction is shown with the flags that it updates. Table 35 Flag Updates Instruction CN1Z – – –...
Page 795: Instruction Timing
(resulting in a minimum PCP core clock cycle time of 5.6ns). When running in 1:1 clocking mode the maximum PCP core clock frequency is the same as the maximum System Peripheral Bus frequency. In the TC1784 the System Peripheral Bus (which is an FPI Bus) is clocked with f , resulting in a minimum PCP core clock cycle time of 11.1ns (in 1:1 clocking mode).
Page 796 TC1784 Peripheral Control Processor (PCP) Table 36 Instruction Timing (cont’d) Instruction Number of Clock Cycles Comments Notes COPY – – EXIT f = 9, s = 7, m = 6 – BCOPY – – FPI Access ADD.F 8 min. 5 int. + 3 min.
Page 797 TC1784 Peripheral Control Processor (PCP) Table 36 Instruction Timing (cont’d) Instruction Number of Clock Cycles Comments Notes LD.P – – – – – – – – – – – – ST.P – – – – – – Immediate Access ADD.I –...
Page 798 TC1784 Peripheral Control Processor (PCP) Table 36 Instruction Timing (cont’d) Instruction Number of Clock Cycles Comments Notes Complex Math DINIT – DSTEP – MINIT – MSTEP.L – MSTEP.U – Jump DEBUG sdb - 0 = 2 – sdb - 1 = exit_time y = 4, n = 2 –...
Page 799: Instruction Encoding
TC1784 Peripheral Control Processor (PCP) 10.19 Instruction Encoding Most instructions are encoded in 16 bits. This allows two instruction to be fetched out of 32 bit instruction memory per access. For example, a COPY and an EXIT instruction can be fetched simultaneously, performing a simple DMA transaction.
Page 800 TC1784 Peripheral Control Processor (PCP) Table 37 Field Definitions (cont’d) Symbol Name Description Exit Count no action Control decrement CNT1 External Debug No External Debug Action caused Action Cause an External Debug Action (breakpoint pin etc.) Entry Point Entry Point on next Channel Invocation:...
Page 801 TC1784 Peripheral Control Processor (PCP) Table 38 Instruction Encoding 0 -:Control fmt Ins DST + - SRC + - CNT0 Size COPY INT EP EC - CONDC B EXIT Condition for Interrupt fmt Ins DST + - SRC + -...
Page 802 TC1784 Peripheral Control Processor (PCP) Table 38 Instruction Encoding (cont’d) error MCLR.PI AND.PI MSET.PI OR.PI XOR.PI LD.PI ST.PI XCH.PI error error error error 3 -:Arithmetic Instruction R[b] R[a] CONDC A COMP error LD.P ST.P error error User´s Manual 10-137 V1.1, 2011-05...
Page 803 TC1784 Peripheral Control Processor (PCP) Table 38 Instruction Encoding (cont’d) 4 - Immediate Instruction R[a] Immediate 6 - bit SUB.I ADD.I COMP.I error LDL.IU following #imm16 instruction LDL.IL following #imm16 instruction LD.I INB.I CHKB error 5 -:FPI Instruction R[a] Immediate 5 - bit...
Page 804 TC1784 Peripheral Control Processor (PCP) Table 38 Instruction Encoding (cont’d) MINIT MSTEP.L MSTEP.U error error error error error error error error error error error 7 -:JUMP op2:Instr Offset 10 - bit op2:Instr CONDC B Offset 6 - bit JC.A Absolute Destination in next...
Page 805: Programming Of The Pcp
TC1784 Peripheral Control Processor (PCP) 10.20 Programming of the PCP In this section, several techniques are outlined to help design channel programs. There are also examples on configuring a channel program’s context. 10.20.1 Initial PC of a Channel Program A channel program can begin operation at the Channel Entry Table location corresponding to the priority of the interrupt.
Page 806: Channel Resume
TC1784 Peripheral Control Processor (PCP) 10.20.1.2 Channel Resume When PCP_CS.RCB = 0, the program counter of the PCP is vectored to the address that is restored from the channel program’s context. This means that before exiting, a channel program must itself arrange for where it will resume execution by configuring the value of its PC in its saved context so that it restarts at the desired location.
Page 807: Channel Management For Small And Minimum Contexts
TC1784 Peripheral Control Processor (PCP) ERROR,cc_NZ ;jump to error routine ;if not correct ADD.I R5,#0x1 ;increment state number EXIT EC=1,ST=0,INT=0,EP=1,cc_UC ;begin exit STATE1: COMP.I R5,#0x1 ;compare to interrupt number ;it should be ERROR,cc_NZ ;jump to error routine ;if not correct ADD.I...
Page 808: Dispatch Of Low Priority Tasks
TC1784 Peripheral Control Processor (PCP) two choices here. A boot-time interrupt channel program can be invoked once to perform initialization, or there can be a program that routinely loads these values as a matter of course, and is invoked at boot time or as upon receipt of the very first interrupt.
Page 809: Case-Like Code Switches (Computed Go-To)
TC1784 Peripheral Control Processor (PCP) 10.20.6 Case-like Code Switches (Computed Go-To) The JC.I instruction can be used to implement a multi-way branch for branch-on-bit or branch-on-state conditional branches. This instruction allows a conditional relative jump based on an index held in a register. If this instruction is combined with a table of jump addresses, a switch-type statement can be implemented.
Page 810: Bcopy Instruction (Burst Copy)
(see the FPI Bus description for details). If either address is incorrectly aligned, the PCP will generate an Illegal Operation Error Exit. See also Page 152 for TC1784 specific details of the BCOPY instruction. User´s Manual 10-145 V1.1, 2011-05...
Page 811: Pcp Programming Notes And Tips
TC1784 Peripheral Control Processor (PCP) 10.21 PCP Programming Notes and Tips This section discusses constraints on the use of the PCP and points out some non- obvious issues. 10.21.1 Notes on PCP Configuration For configuring of the PCP, some notes should be regarded.
Page 812 TC1784 Peripheral Control Processor (PCP) TOS (service request number to use during optional interrupt at channel program EXIT) fields, R6 should not be used to pass values from one invocation of a channel program to the next invocation. • If PRAM is to be accessed programmatically, then R7.DPTR must be configured properly as a pointer into the PRAM.
Page 813: Use Of Channel Interruption
TC1784 Peripheral Control Processor (PCP) 10.21.3 Use of Channel Interruption For channel interruption, the following note should be regarded. • When a channel program consists of only a few instructions, it is best to configure the channel to be non-interruptible. This increases overall efficiency by removing the context save/restore overhead that would be incurred if the channel were to be interruptible.
Page 814: Implementing Divide Algorithms
TC1784 Peripheral Control Processor (PCP) Note: When using this scheme, each channel program must ensure prior to channel exit that the R6.CPPN field contains the appropriate value, so that when the channel is next invoked, it will run at the correct priority.
Page 815: Implementing Multiply Algorithms
TC1784 Peripheral Control Processor (PCP) instructions in the sequence) but the divisor is always 32 bits. Prior to the DINIT instruction, the dividend must always occupy the appropriate most significant bits within the 32-bit dividend register (Rb). Divide Examples Example of a 32/32 bit divide (R5 / R3):...
Page 816 TC1784 Peripheral Control Processor (PCP) R1, 8 ;Rotate least significant byte of R1 ;to most significant byte MINIT R1, R4 ;Initialize ready for multiply MSTEP32 R1, R4 ;Perform one MSTEP32 instruction ;(8 bit multiply) After this sequence, R0 holds the result, R1 is left unchanged (right rotated by RR instruction then left rotated by MSTEP32 instruction), and R4 is unchanged.
Page 817: Implementation Of The Pcp In The Tc1784
The addresses of the PCP registers and memories in the TC1784 are given in the following subsections: 10.22.1 PCP Memories In the TC1784, the location of the registers and the memories sizes of the PRAM and the CMEM are given in Table Table 39...
Page 818: Pcp Reset Operation
PCP Reset Operation The PCP module can be reset by a system hardware signal (hard reset). PCP Hard Reset A PCP hard reset is always triggered if at least one of these TC1784 reset sources becomes active: • Watchdog Timer Reset •...
Page 819: Direct Memory Access Controller (Dma)
Direct Memory Access Controller (DMA) Direct Memory Access Controller (DMA) This chapter describes the Direct Memory Access (DMA) Controller and the Memory Checker Module (MCHK) of the TC1784. It contains the following sections: • Functional description of the DMA controller kernel (see Section 11.2)
Page 820 TC1784 Direct Memory Access Controller (DMA) • The System Interrupt Registers are removed from the DMA module (moved to CPU, SCU and PMU). • The DMA module has now 8 Service Requests nodes in general. DMA interrupt outputs DMA SR[7:0] are connected to interrupt nodes. SR[15:8] are used as DMA channel request inputs (DMA_SRCn (n = 0-7)).
Page 821: Dma Controller Kernel Description
DMA Sub-Block. The Bus Switch provides the connection of the DMA Sub-Blocks to the two On Chip Bus interfaces and a DMA Peripheral interface. In the TC1784, the two On Chip Bus interfaces are connected to the System Peripheral Bus and the LMB Bus.
Page 822: Features
TC1784 Direct Memory Access Controller (DMA) 11.2.1 Features The DMA controller has the following features: • 16 independent DMA channels – 2 DMA Sub-Blocks with (8 DMA channels per DMA Sub-Block) – DMA Sub-Blocks with support of parallel channel execution (1 channel per Sub- Block, both Sub-Blocks in parallel) –...
Page 823: Definition Of Terms
TC1784 Direct Memory Access Controller (DMA) 11.2.2 Definition of Terms Some basic terms must be defined for the functional description of the DMA controller. DMA Move A DMA move is an operation that always consists of two parts: 1. A read move that loads data from a data source into the DMA controller 2.
Page 824: Dma Principles
TC1784 Direct Memory Access Controller (DMA) 11.2.3 DMA Principles The DMA controller supports DMA moves from one address location to another one. DMA moves can be requested either by hardware or by software. DMA hardware requests are triggered by specific request lines from the peripheral modules or from...
Page 825: Dma Channel Functionality
TC1784 Direct Memory Access Controller (DMA) 11.2.4 DMA Channel Functionality Each of the 16 DMA channels has one associated register set containing seven 32-bit registers. These registers are numbered by one index to indicate the related DMA Sub- Block and one index to indicate the related DMA channel: Index “m” refers to the DMA Sub-Block number (m = 0-1) and Index “n”...
Page 826 TC1784 Direct Memory Access Controller (DMA) When writing a new address to the (address of) the source or destination address register and no DMA transaction is running, the new address value is directly written into the source or destination address register. In this case, no buffering of the address is required.
Page 827 TC1784 Direct Memory Access Controller (DMA) Write new source address to (address of) SADRmn Transaction running ? (CHSRmn.TCOUNT != 0 OR TRSR.CHmn = 1) Store new source address intermediately in SHADRmn New transaction started ? & (ADRCRmn.SHCT = 01 Content of SHADR0n is transferred into SADRmn.
Page 828 TC1784 Direct Memory Access Controller (DMA) CHSRmn.TCOUNT tc2-1 tc2-2 tc1-1 CHCRmn.TREL sa1+ sa1+ SADRmn sa1+1 sa2+1 sa2+2 tc1-1 SHADRmn with 0000 0000 ADRCRmn.SHCT= 01 tc1 = transfer count 1 1) 3) = writing to CHCRmn and SADRmn tc2 = transfer count 2...
Page 829: Dma Channel Request Control
TC1784 Direct Memory Access Controller (DMA) 11.2.4.2 DMA Channel Request Control Figure 11-6 shows the control logic for DMA requests that is implemented for each DMA channel. CHCRmn Suspend Request CHMODE TRSR Suspend Control HTREQ TRSR & SUSPMR Reset ECHmn...
Page 830: Dma Channel Operation Modes
TC1784 Direct Memory Access Controller (DMA) Status flag TRSR.CHmn indicates whether or not a software or hardware generated DMA request for DMA channel mn is pending. TRSR.CHmn can be reset by software or by hardware at the end of a DMA transfer (RROAT = 0) or at the end of a DMA transaction (RROAT = 1).
Page 831 TC1784 Direct Memory Access Controller (DMA) When TCOUNT reaches the 0, DMA channel mn becomes disabled and status flag TRSR.CHmn is reset. Setting STREQ.SCHmn again starts a new DMA transaction of DMA channel mn with the parameters as actually defined in the channel register set.
Page 832 TC1784 Direct Memory Access Controller (DMA) Hardware-controlled Modes In hardware-controlled modes, a hardware request signal starts a DMA transaction or a single DMA transfer. There are two hardware-controlled modes available: • Single Mode: Hardware requests are disabled by hardware after a DMA transaction •...
Page 833 TC1784 Direct Memory Access Controller (DMA) CHCRmn.RROAT = 1 TRSR.CHmn TRSR.HTREmn CHmn_REQ DMA Transfer mn TR0 TR1 TR0 TR1 CHSRmn.TCOUNT tc-1 tc-1 tc = initial transfer count (triggered at the end of a transaction with IRDV=0) CHCRmn.RROAT = 0 TRSR.CHmn TRSR.HTREmn...
Page 834: Error Conditions
TC1784 Direct Memory Access Controller (DMA) Combined Software/Hardware-controlled Mode Figure 11-9 shows how software- and hardware-controlled modes can be combined. In the example, the first DMA transfer is triggered by software when setting STREQ.SCHmn. Hardware requests are still disabled. After hardware requests have been enabled by setting HTREQ.ECHmn, subsequent DMA transfers are triggered now...
Page 835: Channel Reset Operation
TC1784 Direct Memory Access Controller (DMA) The transaction lost error flag ERRSR.TRLmn indicates if a DMA request for a DMA channel mn has been lost. In the case of a read error, the write action is not executed, but the destination address is updated.
Page 836: Transfer Count And Move Count
TC1784 Direct Memory Access Controller (DMA) 11.2.4.6 Transfer Count and Move Count The move count determines the number of moves (consisting of one read and one write each) to be done in each transfer. It allows the user to indicate to the DMA the number of moves to be done after one request.
Page 837 TC1784 Direct Memory Access Controller (DMA) Source Memory Destination Memory Moves ..ADRCRmn Parameters: ADRCRmn Parameters: SMF = 011 DMF = 010 INCS = 1 INCD = 0 MCA06159 Figure 11-11 Programmable Address Modification - Example 1 (m = 0-1)
Page 838: Circular Buffer
TC1784 Direct Memory Access Controller (DMA) Source Memory Destination Memory Moves ADRCRmn Parameters: ADRCRmn Parameters: SMF = 000 DMF = 001 INCS = 1 INCD = 1 MCA06160 Figure 11-12 Programmable Address Modification - Example 2 (m = 0-1) 11.2.4.7 Circular Buffer Destination and source address can be configured to build a circular buffer separately for source and destination data.
Page 839: Transaction Control Engine
TC1784 Direct Memory Access Controller (DMA) 11.2.5 Transaction Control Engine Each DMA Sub-Block has a Transaction Control Unit. The Transaction Control Unit in the DMA Sub-Block, as shown in the DMA Controller block diagram in Figure 11-1, contains a Channel Arbiter and a Move Engine.
Page 840: Bus Switch, Bus Switch Priorities
TC1784 Direct Memory Access Controller (DMA) DMA Channels 0n of Sub-Block m DMA Channel Arbiter Move Engine m Transaction Control Unit m Bus Switch MCA06161 Figure 11-13 Transaction Control Engine (m = 0-1) 11.2.6 Bus Switch, Bus Switch Priorities The Bus Switch of the DMA controller provides the connection from the DMA Sub-Blocks...
Page 841 TC1784 Direct Memory Access Controller (DMA) DMA Sub-Block m Move Engine m MLI0 Arbiter/ Memory Bus Switch Switch Checker Control Cerberus Buffer Buffer LMB Bus FPI Bus Interface Interface MCA06162 Figure 11-14 Bus Switch One access can be buffered in the bus interfaces.
Page 842: Dma Module Priorities On On Chip Busses (Fpi Bus, Lmb Bus)
TC1784 Direct Memory Access Controller (DMA) CHCRmn.DMAPRIO value determines the priority on the DMA Bus Switch (see Table 11-2). Table 11-1 DMA Bus Switch Priorities Priority Agent Requests Comment Highest Cerberus to On Chip Bus High Priority selection by software in Cerberus.
Page 843: Dma Module: On Chip Bus Access Rights, Rmw Support
TC1784 Direct Memory Access Controller (DMA) The DMA Module is connected to the FPI Bus and to the LMB Bus with master interfaces. The DMA LMB Master and the DMA FPI Master is each connected with three priorities to its On Chip Bus (low, medium and high priority), where it competes against the other bus masters connected to the On Chip Bus for bus access.
Page 844 TC1784 Direct Memory Access Controller (DMA) The DMA FPI master interface supports: • single data read and write transactions (8bit, 16bit, 32bit) • generation of pipelined FPI transactions from different sources (Move Engines, Cerberus, MLI) • de-assertion of request after retry in order to prevent bus blocking.
Page 845: Dma Module Bridge Functionality
TC1784 Direct Memory Access Controller (DMA) If the next read to a read from a segment 8 address is not identical (64bit aligned) to the actual read buffer contents, the contents of the read buffer is invalidated. A 64bit LMB...
Page 846: On-Chip Debug Capabilities
Peripheral Interface is described in the related module chapters. 11.2.11.2 Soft-suspend Mode The TC1784 on-chip debug control unit is able to generate a Soft-suspend Mode request (SUSREQ) for the DMA controller. When this soft-suspend request becomes active, the state of a DMA channel becomes frozen regarding hardware changes to ensure that the state of the DMA channels can be analyzed by reading the register contents.
Page 847: Break Signal Generation
TC1784 Direct Memory Access Controller (DMA) after Suspend Mode has been left again. Suspend Mode of DMA channel mn is left and its normal operation continues if either the SUSREQ signal becomes inactive, or if the enable bit SUSENmn is reset by software.
Page 848 TC1784 Direct Memory Access Controller (DMA) DMA Sub-Block m OCDSR BRL0 ≥1 & Enabled Transaction Lost Interrupts 00-07 OCDSR OCDSR ≥1 BREAK BCHS0 BTCR0 TRSR CH01 Edge Detection TRSR CH07 MCA06164 Figure 11-16 DMA Break Event Generation (m = 0-1) User´s Manual...
Page 849: Interrupts
10-bit TCOUNT value. This means that a TCOUNT match interrupt can be generated after one of the last 16 DMA transfers of a DMA transaction. Note that with 1) In the TC1784, only SR[7:0] are connected to interrupt nodes. SR[8:15] are used for DMA channel triggering/connections.
Page 850 Enabled if PATSEL ≠ 00 Pattern Detection Interrupt mn MCA06165 Figure 11-17 Channel Interrupts (m = 0-1) 1) In the TC1784, SR[7:0] are connected to interrupt nodes. SR[8:15] are used for DMA channel triggering/connections. User´s Manual 11-32 V1.1, 2011-05 DMA, V3.03...
Page 851: Transaction Lost Interrupt
CTL07 TRL07 ETRL07 CH07 Reset Transaction Lost Interrupt 07 MCA06166 Figure 11-18 Transaction Lost Interrupt 1) In the TC1784 SR[7:0] are connected to interrupt nodes. SR[15:8] are used as DMA channel trigger signals. User´s Manual 11-33 V1.1, 2011-05 DMA, V3.03...
Page 852: Move Engine Interrupts
CME0DER ME0DER EME0DER Move Engine 0 Destination Error Interrupt MCA06167 Figure 11-19 Move Engine Interrupts 1) In the TC1784 SR[7:0] are connected to interrupt nodes. SR[15:8] are used as DMA channel trigger signals. User´s Manual 11-34 V1.1, 2011-05 DMA, V3.03...
Page 853 TC1784 Direct Memory Access Controller (DMA) When a Move Engine 0 source or destination error occurs, additional status bits and bit fields are provided in the error status register ERRSR to indicate the following two status conditions: • At which On Chip Bus interface a Move Engine 0 error occurred (FPI or LMB) •...
Page 854: Wrap Buffer Interrupts
WRPDE Reset Wrap Destination Buffer Interrupt MCA06168 Figure 11-20 DMA Wrap Buffer Interrupts(m = 0-1) 1) In the TC1784 SR[7:0] are connected to interrupt nodes. SR[15:8] are used as DMA channel trigger signals. User´s Manual 11-36 V1.1, 2011-05 DMA, V3.03...
Page 855: Interrupt Request Compressor
SRx. Each interrupt output SR[15:0] can also be activated by writing a 1 to the corresponding bit GINTR.SIDMAx. 1) In the TC1784 SR[7:0] are connected to interrupt nodes. SR[15:8] are used as DMA channel trigger signals. User´s Manual 11-37 V1.1, 2011-05...
Page 856: Pattern Detection
TC1784 Direct Memory Access Controller (DMA) CHICRmn CHICRmn INTP SIDMA0 ≥1 MEm DMA Channel To SR1 Interrupt Interrupts (8) & Output Pattern Det. Interrupts (8) To SR14 TRLINP To SR1 MEm Transaction Lost Interrupts (1) To SR14 MEmINP To SR1...
Page 857 TC1784 Direct Memory Access Controller (DMA) As the compare match patterns are stored in the Move Engine 0 (register ME0PR), its compare patterns are used for all DMA channels that are assigned to Move Engine 0 (all DMA channels of the DMA Sub-Block 0.
Page 858: Pattern Compare Logic
TC1784 Direct Memory Access Controller (DMA) 11.2.13.1 Pattern Compare Logic Read move data and compare match patterns are compared on a bit-wise level. The logic as shown in Figure 11-22 is implemented in each COMP block of Figure 11-23, Figure...
Page 859: Pattern Detection For 8-Bit Data Width
TC1784 Direct Memory Access Controller (DMA) 11.2.13.2 Pattern Detection for 8-bit Data Width When 8-bit channel data width is selected (CHCRmn.CHDW = 00 ), the pattern detection logic is configured as shown in Figure 11-23. Three compare match configurations are possible.
Page 860: Pattern Detection For 16-Bit Data Width
TC1784 Direct Memory Access Controller (DMA) 11.2.13.3 Pattern Detection for 16-bit Data Width When 16-bit channel data width is selected (CHCRmn.CHDW = 01 ) the pattern detection logic can be configured as shown in Figure 11-24. Three compare match configurations are possible.
Page 861 TC1784 Direct Memory Access Controller (DMA) mode that combines the pattern search capability for aligned and unaligned 16-bit data searches. ADRCRmn CHCRmn ME0PR PAT03 PAT02 PAT01 PAT00 INCS PATSEL Mask COMP Pattern Detected Mask ≥1 COMP & Mask COMP ME0R...
Page 862: Pattern Detection For 32-Bit Data Width
TC1784 Direct Memory Access Controller (DMA) 11.2.13.4 Pattern Detection for 32-bit Data Width When 32-bit channel data width is selected (CHCRmn.CHDW = 10 ) the pattern detection logic is configured as shown in Figure 11-25. Three compare match configurations are possible.
Page 863: Access Protection
The two parameters (SIZE, SLICE) of the four address range extensions of a move engine are numbered by index “n” (n = 0-3). In the TC1784 the number “a” is defined in the followign way: User´s Manual 11-45 V1.1, 2011-05...
Page 864 Note: The definition of the fixed address ranges x and the assignment of each sub-range to one of the fixed address ranges is product-specific. The definitions of the address ranges for the DMA controller as implemented in the TC1784 are defined Page 11-112.
Page 865 TC1784 Direct Memory Access Controller (DMA) Fixed Address Range a a-1 Fixed Address Variable Address Assigned for AENx x = 0-31 Programmable Address Range Extension SIZE = 111 Fixed Address Variable Address SIZE = 110 Fixed Address Variable Address SIZE = 101...
Page 866: Dma Module Registers
Table 11-29. All DMA kernel register names described in this section are also referenced in other parts of the TC1784 User´s Manual by the module name prefix “DMA_”. The registers are numbered by one index to indicate the related DMA Sub-Block and one index to indicate the related DMA channel: Index “m”...
Page 867 TC1784 Direct Memory Access Controller (DMA) Table 11-8 Registers Overview - DMA Control Registers Short Description Offset Access Mode Reset Description Name Addr. Class Read Write DMA_CLC DMA Clock Control U, SV SV, E Page 11-122 Register Reserved DMA_ID DMA Module...
Page 868 TC1784 Direct Memory Access Controller (DMA) Table 11-8 Registers Overview - DMA Control Registers Short Description Offset Access Mode Reset Description Name Addr. Class Read Write DMA_ME1 DMA Move Engine 1 U, SV SV Page 11-81 Pattern Register DMA_ DMA Move Engine 0...
Page 869 TC1784 Direct Memory Access Controller (DMA) Table 11-8 Registers Overview - DMA Control Registers Short Description Offset Access Mode Reset Description Name Addr. Class Read Write DMA_CHC DMA Channel mn (n x 20 U, SV SV Page 11-86 Control Register...
Page 870 TC1784 Direct Memory Access Controller (DMA) Table 11-8 Registers Overview - DMA Control Registers Short Description Offset Access Mode Reset Description Name Addr. Class Read Write Reserved DMA_ DMA MLI0 Service U, SV SV Page 11-124 MLI0SRC3 Request Control Reg.
Page 871 TC1784 Direct Memory Access Controller (DMA) 2) Write access mode to DMA_SHADRmn is controlled by the register bit DMA_ADRCRmn.SHWEN. DMA_ADRCRmn.SHWEN=´0´ -> Access Mode Write DMA_SHADRmn DMA_ADRCRmn.SHWEN=´1´ -> Access Mode Write for DMA_SHADRmn is SV. Note: Register bits marked “w” in the following register description are virtual registers and do not contain flip-flops.
Page 872: System Registers
TC1784 Direct Memory Access Controller (DMA) 11.3.1 System Registers DMA Module Identification Register. DMA_ID Module Identification Register (008 Reset Value: 001A C0XX MOD_NUMBER MOD_TYPE MOD_REV Field Bits Type Description MOD_REV [7:0] Module Revision Number This bit field defines the module revision number.
Page 873 TC1784 Direct Memory Access Controller (DMA) DMA_OCDSR DMA OCDS Register (064 Reset Value: 0000 0000 BCHS1 BTRC1 BCHS0 BTRC0 Field Bits Type Description BTRC0 [1:0] Break Trigger Condition In Sub-Block 0 This bit field determines the transition type for the transaction request bit TRSR.CH0n that leads to a...
Page 874 TC1784 Direct Memory Access Controller (DMA) Field Bits Type Description BRL0 Break On Request Lost in Sub-Block 0 This bit field determines whether a BREAK signal is generated for DMA Sub-Block 0 when at least one of its eight transaction lost interrupts becomes active.
Page 875 TC1784 Direct Memory Access Controller (DMA) The Suspend Mode Register contains bits for each DMA channel that make it possible to enable/disable its Soft-suspend Mode capability and that indicate its suspend status. DMA_SUSPMR DMA Suspend Mode Register (068 Reset Value: 0000 0000...
Page 876 TC1784 Direct Memory Access Controller (DMA) Field Bits Type Description SUSEN1n Suspend Enable for DMA Channel 1n (n = 0-7) This bit enables the soft suspend capability individually for each DMA channel 1n. DMA channel 1n is disabled for Soft-suspend Mode.
Page 877 DMA interrupt output line SRx will be activated. Reading this bit returns a 0 [31:16] Reserved Read as 0; should be written with 0. Note: In the TC1784, SR[7:0] are connected to interrupt nodes. SR[15:8] are used as DMA channel request inputs (Page 11-102). User´s Manual 11-59 V1.1, 2011-05...
Page 878: General Control/Status Registers
TC1784 Direct Memory Access Controller (DMA) 11.3.2 General Control/Status Registers The bits in the Channel Reset Request Register are used to reset DMA channel mn. DMA_CHRSTR DMA Channel Reset Request Register (010 Reset Value: 0000 0000 Field Bits Type Description...
Page 879 TC1784 Direct Memory Access Controller (DMA) The bits in the Transaction Request State Register indicates which DMA channel is processing a request, and which DMA channel has hardware transaction requests enabled. DMA_TRSR DMA Transaction Request State Register (014 Reset Value: 0000 0000...
Page 880 TC1784 Direct Memory Access Controller (DMA) Field Bits Type Description HTRE1n 24+n Hardware Transaction Request Enable State of DMA (n = 0-7) Channel 1n Hardware transaction request for DMA Channel 1n is disabled. An input DMA request will not trigger the channel 1n.
Page 881 TC1784 Direct Memory Access Controller (DMA) The bits in the Software Transaction Request Register are used to generate a DMA transaction request by software. DMA_STREQ DMA Software Transaction Request Register (018 Reset Value: 0000 0000 Field Bits Type Description SCH0n...
Page 882 TC1784 Direct Memory Access Controller (DMA) The bits in the Hardware Transaction Request Register enable or disable DMA hardware requests. DMA_HTREQ DMA Hardware Transaction Request Register (01C Reset Value: 0000 0000 Field Bits Type Description ECH0n Enable Hardware Transfer Request...
Page 883 TC1784 Direct Memory Access Controller (DMA) Table 11-9 Conditions to Set/Reset the Bits TRSR.HTREmn (cont’d) HTREQ.ECHmn HTREQ.DCHmn Transaction Finishes Modification of for Channel mn TRSR.HTREmn Reset Reset 1) In Single Mode only. In Continuous Mode, the end of a transaction has no impact.
Page 884 TC1784 Direct Memory Access Controller (DMA) The Enable Error Register describes how the DMA controller reacts to errors. It enables the interrupts for the loss of a transaction request or Move Engine errors. DMA_EER DMA Enable Error Register (020 Reset Value: 0000 0000...
Page 885 0001 SR1 selected for Move Engine 0 interrupt … … 1111 SR15 selected for Move Engine 0 interrupt Note: In the TC1784, SR[7:0] are connected to interrupt nodes. SR[15:8] are used as DMA channel request inputs (Page 11-102). User´s Manual 11-67 V1.1, 2011-05...
Page 886 0001 SR1 selected for Move Engine 1 interrupt … … 1111 SR15 selected for Move Engine 1 interrupt Note: In the TC1784, SR[7:0] are connected to interrupt nodes. SR[15:8] are used as DMA channel request inputs (Page 11-102). TRLINP [31:28] rw...
Page 887 TC1784 Direct Memory Access Controller (DMA) The Error Status Register indicates if the DMA controller could not answer to a request because the previous request was not terminated (see Section 11.2.4.4). It indicates also the FPI Bus accesses that have been terminated with errors.
Page 888 TC1784 Direct Memory Access Controller (DMA) Field Bits Type Description ME0SER Move Engine 0 Source Error This bit is set whenever a Move Engine 0 error occurred during a source (read) move of a DMA transfer, or a request could not been serviced due to the access protection.
Page 889 TC1784 Direct Memory Access Controller (DMA) Field Bits Type Description LMBER LMB Error This bit is set whenever a move that has been started by the DMA/MLI LMB master interface leads to an error on the LMB Bus. No error occurred.
Page 890 TC1784 Direct Memory Access Controller (DMA) The Clear Error contains bits that make it possible to clear the Transaction Request Lost flags or the Move Engine error flags. DMA_CLRE DMA Clear Error Register (028 Reset Value: 0000 0000 FPIE MLI0...
Page 891 TC1784 Direct Memory Access Controller (DMA) Field Bits Type Description CME1DER Clear Move Engine 1 Destination Error No action Clear destination error flag ERRSR.ME1DER. CFPIER Clear FPI Error No action Clear error flag ERRSR.FPIER. CLMBER Clear LMB Error No action Clear error flag ERRSR.LMBER.
Page 892 TC1784 Direct Memory Access Controller (DMA) The Interrupt Status Register indicates if CHSRmn.TCOUNT matches with CHCRmn.IRDV, or if CHSRmn.TCOUNT has been decremented (depending on CHICRmn.INTCT[0]),or if a pattern has been detected. These conditions can also generate an interrupt if enabled (see...
Page 893 TC1784 Direct Memory Access Controller (DMA) Field Bits Type Description IPM0n 16+n Pattern Detection from Channel 0n (n = 0-7) This bit indicates that a pattern has been detected for channel 0n while the pattern detection has been enabled. This bit (and ICH0n) is reset by software when writing a 1 to INTCR.CICH0n or by a channel...
Page 894 TC1784 Direct Memory Access Controller (DMA) The Wrap Status Register gives information about the channels that did a wrap-around on their source or destination buffer(s). This condition can also lead to an interrupt if it is enabled. DMA_WRPSR DMA Wrap Status Register...
Page 895 TC1784 Direct Memory Access Controller (DMA) Field Bits Type Description WRPD1n 24+n Wrap Destination Buffer for Channel 1n (n = 0-7) These bits indicate which channels have done a wrap-around of their destination buffer(s). No wrap-around occurred for channel 1n.
Page 896 TC1784 Direct Memory Access Controller (DMA) The bits in the Interrupt Clear Register make it possible to reset the channel interrupt flags and the wrap buffer interrupt flags for DMA Channels mn. DMA_INTCR DMA Interrupt Clear Register (058 Reset Value: 0000 0000...
Page 897: Move Engine Registers
TC1784 Direct Memory Access Controller (DMA) Field Bits Type Description CWRP1n 24+n Clear Wrap Buffer Interrupt for DMA Channel 1n (n = 0-7) These bits make it possible to reset the wrap source buffer interrupt flag WRPSR.WRPS1n and the wrap destination buffer interrupt flag WRPSR.WRPD1n...
Page 898 [7:5] Read Buffer Trace for FPI Bus Interface This bit field contains trace information from the buffer in the FPI Bus Interface. In the TC1784 it indicates the source of a bus access to the FPI Bus. Default value. DMA Move Engine 0...
Page 899 TC1784 Direct Memory Access Controller (DMA) The Move Engine 0 Read Register indicates the value that has just been read by Move Engine 0. The value in this register is compared to the bits in register ME0PR according to the bit fields CHCRmn.PATSEL.
Page 900 TC1784 Direct Memory Access Controller (DMA) Field Bits Type Description PAT00, [7:0], Pattern for Move Engine 0 PAT01, [15:8], Determines up to four 8-bit compare patterns/mask PAT02, [23:16], patterns to be processed by the pattern detection PAT03 [31:24] logic in Move Engine 0. Depending on the pattern detection configuration (CHCR0n.PATSEL) and...
Page 901 If AENx = 0 for a read/write move to address range x, the read/write move is not executed and a source/destination Move Engine interrupt is generated. Note: See Table 11-13 Page 11-112 for the TC1784-specific address range definition. User´s Manual 11-83 V1.1, 2011-05 DMA, V3.03...
Page 902 TC1784 Direct Memory Access Controller (DMA) The DMA Move Engine 0 Access Range Register determines number and size of the sub-ranges for address range extension n (n = 0-3). See also Figure 11-26 for bit field definitions. DMA_ME0ARR DMA Move Engine 0 Access Range Register...
Page 903 3. SIZE3 [31:29] Address Size 3 SIZE3 determines the sub-range size within address range extension 3. Note: See Section 11.4.2 Page 11-112 for the TC1784-specific address range and address range extension definitions. User´s Manual 11-85 V1.1, 2011-05 DMA, V3.03...
Page 904: Channel Control/Status Registers
TC1784 Direct Memory Access Controller (DMA) 11.3.4 Channel Control/Status Registers The Channel Control Register for DMA channel mn contains its configuration and its control bits and bit fields. DMA_CHCR0x (x = 0-7) DMA Channel 0x Control Register (084 +x*20 Reset Value: 0000 0000...
Page 905 TC1784 Direct Memory Access Controller (DMA) Field Bits Type Description PRSEL [15:12] Peripheral Request Select This bit field controls the hardware request input multiplexer of DMA channel mn (see Figure 11-6 Page 11-11). 0000 Input CHmn_REQI0 selected 0001 Input CHmn_REQI1 selected...
Page 906 TC1784 Direct Memory Access Controller (DMA) Field Bits Type Description CHMODE Channel Operation Mode CHMODE determines the reset condition for control bit TRSR.HTREmn of DMA channel mn. Single Mode operation is selected for DMA channel mn. After a transaction, DMA channel mn is disabled for further hardware requests (TRSR.HTREmn is reset by hardware)
Page 907 TC1784 Direct Memory Access Controller (DMA) Field Bits Type Description CHPRIO Channel Priority CHPRIO determines the priority of DMA channel n for the Move Engine minternal channel arbitration. This priority is used for the case when multiple channels of Move Engine m are triggered in parallel.
Page 908 TC1784 Direct Memory Access Controller (DMA) The Channel Status Register contains the current transfer count and a pattern detection compare result. DMA_CHSR0x (x = 0-7) DMA Channel 0x Status Register (080 +x*20 Reset Value: 0000 0000 DMA_CHSR1x (x = 0-7)
Page 909 TC1784 Direct Memory Access Controller (DMA) The Channel Interrupt Control Register controls the interrupts generation. DMA_CHICR0x (x = 0-7) DMA Channel 0x Interrupt Control Register (088 +x*20 Reset Value: 0000 0000 DMA_CHICR1x (x = 0-7) DMA Channel 1x Interrupt Control Register...
Page 910 SR1 selected for channel mx wrap buffer interrupt … … 1111 SR15 selected for channel mx wrap buffer interrupt Note: In the TC1784, SR[7:0] are connected to interrupt nodes. SR[15:8] are used as DMA channel request inputs (Page 11-102). INTP [11:8]...
Page 911 TC1784 Direct Memory Access Controller (DMA) The Address Control Register controls how source and destination addresses are updated after a DMA move. Furthermore, it determines whether or not a source or destination address register update is shadowed. DMA_ADRCR0x (x = 0-7)
Page 912 TC1784 Direct Memory Access Controller (DMA) Field Bits Type Description INCS Increment of Source Address This bit determines whether the address offset as selected by SMF will be added to or subtracted from the source address after each DMA move. The source...
Page 913 TC1784 Direct Memory Access Controller (DMA) Field Bits Type Description CBLS [11:8] Circular Buffer Length Source This bit field determines which part of the 32-bit source address register remains unchanged and is not updated after a DMA move operation (see also Section 11.2.4.7).
Page 914 TC1784 Direct Memory Access Controller (DMA) Field Bits Type Description SHCT [17:16] rw Shadow Control This bit field determines whether an address is transferred into the shadow address register when writing to source or destination address register. Shadow address register not used. Source and...
Page 915 TC1784 Direct Memory Access Controller (DMA) Table 11-10 shows the offset values that are added or subtracted to/from a source or destination address register after a DMA move. Bit field SMF and bit INCS determine the offset value for the source address. Bit field DMF and bit INCD determine the offset value for the destination address.
Page 916: Channel Address Registers
TC1784 Direct Memory Access Controller (DMA) 11.3.5 Channel Address Registers The Source Address Register contains the 32-bit source address. If a DMA channel mn is active, SADRmn is updated continuously (if programmed) and shows the actual source address that is used for read moves within DMA transfers.
Page 917 TC1784 Direct Memory Access Controller (DMA) The Destination Address Register contains the 32-bit destination address. If a DMA channel is active, DADRmn is updated continuously (if programmed) and shows the actual destination address that is used for write moves within DMA transfers.
Page 918 TC1784 Direct Memory Access Controller (DMA) The Shadow Address Register holds the shadowed source or destination address before it is written into the source or destination address register. SHADRmn can be read only. DMA_SHADR0x (x = 0-7) DMA Channel 0x Shadow Address Register...
Page 919: Dma Module Implementation
TC1784 Direct Memory Access Controller (DMA) 11.4 DMA Module Implementation This section describes the TC1784 DMA module interfaces with the clock control, interrupt control, and address decoding. Figure 11-28 shows the TC1784-specific implementation details and interconnections of the DMA module. The DMA module is supplied with a separate clock control, address decoding, interrupt control, and the request input wiring matrix.
Page 920: Dma Request Wiring Matrix
TC1784 Direct Memory Access Controller (DMA) 11.4.1 DMA Request Wiring Matrix The DMA request input lines of each DMA channel within DMA Sub-Block 0 and DMA Sub-Block 1 are connected to request output lines from the peripheral modules according to Table 11-11.
Page 921 TC1784 Direct Memory Access Controller (DMA) Table 11-11 DMA Request Assignment for DMA Sub-Block 0 (cont’d) DMA Request Line DMA Requesting Unit Selected by Channel GPTA_TRIG01 GPTA CHCR01.PRSEL = 1001 GPTA_TRIG11 GPTA CHCR01.PRSEL = 1010 TINT0SRC ERAY CHCR01.PRSEL = 1011 Reserved CHCR01.PRSEL = 1100...
Page 922 TC1784 Direct Memory Access Controller (DMA) Table 11-11 DMA Request Assignment for DMA Sub-Block 0 (cont’d) DMA Request Line DMA Requesting Unit Selected by Channel MLI0_SR7 MLI0 CHCR03.PRSEL = 0111 STMIRQ0 CHCR03.PRSEL = 1000 GPTA_TRIG03 GPTA CHCR03.PRSEL = 1001 GPTA_TRIG13 GPTA CHCR03.PRSEL = 1010...
Page 923 TC1784 Direct Memory Access Controller (DMA) Table 11-11 DMA Request Assignment for DMA Sub-Block 0 (cont’d) DMA Request Line DMA Requesting Unit Selected by Channel ASC1_TDR ASC1 CHCR05.PRSEL = 0101 MSC0_SR3 MSC0 CHCR05.PRSEL = 0110 MLI0_SR5 MLI0 CHCR05.PRSEL = 0111 STMIRQ0 CHCR05.PRSEL = 1000...
Page 924 TC1784 Direct Memory Access Controller (DMA) Table 11-11 DMA Request Assignment for DMA Sub-Block 0 (cont’d) DMA Request Line DMA Requesting Unit Selected by Channel ADC_SR07 CHCR07.PRSEL = 0011 SSC1_RDR SSC1 CHCR07.PRSEL = 0100 ASC1_RDR ASC1 CHCR07.PRSEL = 0101 CAN_INT_O1 MultiCAN CHCR07.PRSEL = 0110...
Page 925 TC1784 Direct Memory Access Controller (DMA) Table 11-12 DMA Request Assignment for DMA Sub-Block 1 (cont’d) DMA Request Line DMA Requesting Unit Selected by Channel GPTA_TRIG00 GPTA CHCR00.PRSEL = 1001 GPTA_TRIG10 GPTA CHCR00.PRSEL = 1010 INT1SRC ERAY CHCR00.PRSEL = 1011...
Page 926 TC1784 Direct Memory Access Controller (DMA) Table 11-12 DMA Request Assignment for DMA Sub-Block 1 (cont’d) DMA Request Line DMA Requesting Unit Selected by Channel MLI0_SR6 MLI0 CHCR02.PRSEL = 0111 STMIRQ0 CHCR02.PRSEL = 1000 GPTA_TRIG02 GPTA CHCR02.PRSEL = 1001 GPTA_TRIG12 GPTA CHCR02.PRSEL = 1010...
Page 927 TC1784 Direct Memory Access Controller (DMA) Table 11-12 DMA Request Assignment for DMA Sub-Block 1 (cont’d) DMA Request Line DMA Requesting Unit Selected by Channel ASC0_TDR ASC0 CHCR04.PRSEL = 0101 MSC0_SR2 MSC0 CHCR04.PRSEL = 0110 MLI0_SR4 MLI0 CHCR04.PRSEL = 0111 STMIRQ0 CHCR04.PRSEL = 1000...
Page 928 TC1784 Direct Memory Access Controller (DMA) Table 11-12 DMA Request Assignment for DMA Sub-Block 1 (cont’d) DMA Request Line DMA Requesting Unit Selected by Channel ADC_SR06 CHCR06.PRSEL = 0011 SSC0_RDR SSC0 CHCR06.PRSEL = 0100 ASC0_RDR ASC0 CHCR06.PRSEL = 0101 CAN_INT_O0 MultiCAN CHCR06.PRSEL = 0110...
Page 929 TC1784 Direct Memory Access Controller (DMA) 1) GPTA_TRIG signals are per default level sensitive signals while a DMA channel is activated with every active request signal cycle. The DMA internal positive edge detection will generate the channel request with the rising edge of the GPTA_TRIG signal, if selected.
Page 930: Access Protection Assignment
DMA access protection as described on Page 11-45 requires the assignment of 32 fixed address range. Table 11-13 shows this address range assignment as implemented in the TC1784 (see also: Page 11-82, Page 11-82). Table 11-13 DMA Access Protection Address Ranges...
Page 931 TC1784 Direct Memory Access Controller (DMA) Table 11-13 DMA Access Protection Address Ranges (cont’d) Access Protection Range Related Module(s) No. n Enable Bit in Selected Address Range MEmAENR AEN20 F010 C100 - F010 C1FF F01E 8000 - F01E FFFF F024 0000...
Page 932 TC1784 Direct Memory Access Controller (DMA) In the TC1784, four internal memory areas (SPRAM and LDRAM, PRAM, and OVRAM) are protected by an address range verification in addition to the access enable bits. The address range verification is based on the bit fields SIZEx and SLIZEx (x = 3-0), which are located in the registers MEmARR (m = 1-0).
Page 933 TC1784 Direct Memory Access Controller (DMA) SIZE0 and SLICE0 bit fields: PMI sub-range access protection Bit fields SIZE0 and SLICE0 for the PMI memory sub-range access protection (40 KB SPRAM) as shown in Table 11-14. The PMI memory is protected with a min. granularity of 0.5 KB up to the end address...
Page 934 TC1784 Direct Memory Access Controller (DMA) Table 11-14 PMI Address Protection Sub-Range Definition (cont’d) SIZE0 Sub-Ranges SLICE0 Selected Address Range 2 sub-ranges of XXXX0 xxxx 0000 - xxxx 7FFF 32 Kbytes XXXX1 xxxx 8000 - xxxx FFFF 64 Kbytes XXXXX...
Page 935 TC1784 Direct Memory Access Controller (DMA) Table 11-15 OVRAM Address Protection Sub-Range Definition (cont’d) SIZE1 Sub-Ranges SLICE1 Selected Address Range 8 sub-ranges of XX000 xxx0 0000 - xxx0 1FFF 8 Kbytes XX001 xxx0 2000 - xxx0 3FFF … … XX111...
Page 936 TC1784 Direct Memory Access Controller (DMA) Table 11-16 DMI Address Protection Sub-Range Defintions (cont’d) SIZE2 Sub-Ranges SLICE2 Selected Address Range 16 sub-ranges of X0000 xxx0 0000 - xxx0 1FFF 8 Kbytes X0001 xxx0 2000 - xxx0 3FFF … … X1111...
Page 937 TC1784 Direct Memory Access Controller (DMA) Table 11-17 PCP PRAM Address Protection Sub-Range DefintionScheme SIZE3 Sub-Ranges SLICE3 Selected Address Range 32 sub-ranges of 00000 F005 0000 - F005 07FF 2 Kbytes 00001 F005 0800 - F005 0FFF … … 11111...
Page 938: Implementation-Specific Dma Registers
TC1784 Direct Memory Access Controller (DMA) 11.4.3 Implementation-specific DMA Registers The DMA controller as implemented in the TC1784 contains the following additional registers: • DMA clock control register • Service request control registers for DMA controller interrupts (DMA_SRCx) • Service request control registers for MLI module interrupts (DMA_MLI0ySRC.x) Figure 11-29 provides an overview of these registers.
Page 939 TC1784 Direct Memory Access Controller (DMA) The DMA controller module contains in total 12 interrupt request nodes with its interrupt service request control registers: • Eight interrupt requests SR[7:0] = INT_O[7:0] from the DMA controller; upper eight interrupt requests of the DMA controller INT_O[15:8] are used ad DMA channel trigger inputs •...
Page 940: Clock Control Register
TC1784 Direct Memory Access Controller (DMA) 11.4.3.1 Clock Control Register The Clock Control Register controls the DMA module internal clock signal. This clock is also used for the MLI modules as a common clock that can be individually divided for the MLI modules.
Page 941: Dma Interrupt Registers
Direct Memory Access Controller (DMA) 11.4.3.2 DMA Interrupt Registers In the TC1784, the lower eight DMA controller interrupts SR[7:0] are connected to service request control registers. The upper eight DMA controller interrupt outputs SR[15:8] are used as DMA channel request inputs (Page 11-102).
Page 942: Mli Interrupt Registers
TC1784 Direct Memory Access Controller (DMA) 11.4.3.3 MLI Interrupt Registers The Service Request Control Registers of the MLI module is located inside the DMA address area, because the MLI module does not have its own FPI Bus interface. The MLI module shares one FPI Bus slave interface with the DMA controller.
Page 943: Address Map
TC1784 Direct Memory Access Controller (DMA) 11.4.4 Address Map The DMA controller register block address map is shown in Figure 11-31. It shows how the different register blocks are arranged and adds the absolute address information. DMA Service Request Control Registers...
Page 944: Memory Checker Module
TC1784 Direct Memory Access Controller (DMA) 11.5 Memory Checker Module The Memory Checker Module (MCHK) includes two parallel Cyclic Redundancy Checkers (CRCs) that can be used to check the data consistency of two memories in parallel. 11.5.1 Functional Description The Memory Checker module is connected to the DMA Peripheral Interface and can be accessed via the SPB.
Page 945 TC1784 Direct Memory Access Controller (DMA) MCHKIR: memory checker input data bits MCHKRR: memory checker result data bits & AND result bits with polynomial bits in MCHKPOR XOR all bits MCHK_structure Figure 11-32 Implementation of the Memory Checker algorithm User´s Manual 11-127 V1.1, 2011-05...
Page 946: Memory Checker Module Registers
TC1784 Direct Memory Access Controller (DMA) 11.5.2 Memory Checker Module Registers This section describes the kernel registers of the Memory Checker module. MCHK Register Overview Other Registers Module Register Memory Checker Registers MCHK_WR MCHK_ID MCHK_IR0 MCHK_RR0 mchk_ reg_its MCHK_IR1 MCHK_RR1...
Page 947: Memory Checker Module Control Registers
TC1784 Direct Memory Access Controller (DMA) Table 11-19 Registers Overview - Memory Checker Module Control Registers Short Name Description Offset Access Mode Reset Description Addr. Class Read Write MCHK_WR Memory Checker U, SV U, SV Page 11-131 Write Register Reserved...
Page 948 TC1784 Direct Memory Access Controller (DMA) A Memory Checker Input Register is used during write moves of a memory checker related DMA transaction as data destination with its fixed register address. If the DMA moves to register, for example MCHK_IR0 are 8-bit or 16-bit wide, the unused register bits of the 32-bit MCHKIN0 value are taken as 0s for the current result calculation.
Page 949 DMA controller via the Bus Switch of the DMA controller (see Figure 11-14) does not request the two FPI buses of the TC1784, SPB and DMA, because it is near the MLI modules address ranges. MCHK_WR Memory Checker Write Register...
Page 950 TC1784 Direct Memory Access Controller (DMA) User´s Manual 11-132 V1.1, 2011-05 DMA, V3.03...
Page 951: Lmb External Bus Unit
LMB External Bus Unit LMB External Bus Unit (EBU) The External Bus Unit (EBU) of the TC1784 controls the transactions between external memories or peripheral units, and the internal memories and peripheral units. The EBU will only be available for either bare die or parts in BGA packages. The basic interfaces...
Page 952 TC1784 LMB External Bus Unit Address/ Data Path Data Control Asynchronous Control Access Lines State Machine Registers Local Data Memory Region Selection Address Address Address Path Control External Bus Unit EBU MCB05713 Figure 12-2 EBU Block Diagram The EBU takes LMB transactions and translates them into the appropriate external access(es).
Page 953: Ebu Interface Signals
TC1784 LMB External Bus Unit 12.3 EBU Interface Signals The external EBU interface signals are listed in Table 12-1 below. Table 12-1 EBU Interface Signals Signal/Pin Type Function AD[15:0] Multiplexed Address/Data bus lines 0-15 A[20:16] Address bus lines 16-20 CS[3:0]...
Page 954: Read/Write Control Lines, Rd, Rd/Wr
TC1784 LMB External Bus Unit 12.3.4 Read/Write Control Lines, RD, RD/WR Two lines are provided to trigger the read (RD) and write (RD/WR) operations of external devices. While some read/write devices require both signals, there are devices with only one control input. The RD/WR line is then used for these devices. This line will go to an active-low level on a write, and will stay inactive high on a read.
Page 955: Wait Input, Wait
TC1784 LMB External Bus Unit Table 12-3 Byte Control Signal Timing Options (cont’d) Mode EBU_BUSCONx. Description BCGEN Control Mode BCx signals have the same timing as the generated control signals RD or RD/WR. Write Enable Mode 10 BCx signals have the same timing as the generated control signal RD/WR.
Page 956: Control Of Pad Pull Up And Pull Down
TC1784 LMB External Bus Unit 1) If the EBU is disabled by writing 00 to the EBUCON.ARBMODE field, there will be a delay before the signals become available for GPIO usage as the EBU will wait for all pending external memory accesses to be completed and the arbitration logic to return to the “nobus”...
Page 957: External Bus Arbitration
TC1784 LMB External Bus Unit 12.4 External Bus Arbitration The TC1784 memory controller does not support arbitration for the external memory bus. However, the EBU_MODCON.ARBMODE field can be used to disable the memory controller. Table 12-6 lists the programmable parameters for the external bus arbitration.
Page 958: Arbitration Modes
TC1784 LMB External Bus Unit Table 12-6 External Bus Arbitration Programmable Parameters Parameter Function Description EBU_MODCON.ARBMODE Arbitration mode selection Page 12-8 EBU_MODCON.ARBSYNC Arbitration input signal sampling control EBU_MODCON.EXTLOCK External bus ownership locking control EBU_MODCON.TIMEOUTC External bus time-out control Of these only EBU_MODCON.ARBMODE has any effect in the implementation. The others must be left at default values.
Page 959: Start-Up/Boot Process
TC1784 LMB External Bus Unit 12.5 Start-Up/Boot Process After reset, the EBU will be configured with access to the external bus disabled(i.e. no access from LMB to external memory is possible without EBU re-configuration). Only the register space will be accessible.
Page 960: External Busoperation
Note: Not all memory types supported by the memory controller are known to be available in Automotive quality grades. Each TC1784 internal LMB master can access external devices via the EBU. The EBU provides four user-programmable external memory regions. Each of these regions is provided with a set of registers that determine the parameters of the external bus transaction and one chip select signal.
Page 961: External Memory Regions
12.7.1 External Memory Regions The EBU of the TC1784 supports four memory regions, which have their own associated chip select outputs CS[3:0]. Each of these regions has a set of control registers to specify the type of memory/peripheral device and the access parameters.
Page 962 TC1784 LMB External Bus Unit Table 12-8 EBU Address Regions, Registers and Chip Selects Region Associated Address Select Bus Access Chip Registers Configuration Parameters Select Registers Registers Region 0 EBU_ADDRSEL0 EBU_BUSRCON0 EBU_BUSRAP0 EBU_BUSWCON0 EBU_BUSWAP0 Region 1 EBU_ADDRSEL1 EBU_BUSRCON1 EBU_BUSRAP1 EBU_BUSWCON1...
Page 963 TC1784 LMB External Bus Unit Table 12-9 Programmable Parameters of Regions Register Parameter Function (Bit/Bit field) EBU_ADDRSELx ALTSEG Alternate segment of region to be compared to LMB address bits [31:28]. BASE Region base address to be compared with LMB address in conjunction with the MASK parameter.
Page 964: Chip Select Control
TC1784 LMB External Bus Unit 12.7.2 Chip Select Control The EBU generates four chip select signals, CSx, which are all available at dedicated chip select outputs. 12.7.3 Programmable Device Types Each CS region (0 to 3) can be individually configured using the EBU_BUSCONx.AGEN...
Page 965 TC1784 LMB External Bus Unit Table 12-11 Pins used to connect Multiplexed Devices to Memory Controller Memory Memory Controller Device Configuration Device Pins Configuration A(20:16) AD(15:0) 16-bit MUX A(20:16) A(15:0)/ 16-bit Multiplexed D(15:0) Memory/Peripheral Configuration 1) These pins are always outputs which are connected to address pins on the Multiplexed device(s)
Page 966 TC1784 LMB External Bus Unit AD(15:0) A(n:16) RD/WR WAIT Memory Interface Burst FLASH Mem. Figure 12-3 Connection of a 16-bit Multiplexed Device to the Memory Controller User´s Manual 12-16 V1.1, 2011-05 EBUT13L-A, V1.16...
Page 967: Address Comparison
TC1784 LMB External Bus Unit 12.7.4 Address Comparison Standard Address Comparison Mode When an Addressing Override Mode is not active, each of the four EBU regions can be programmed for independent base addresses and lengths by bits and bit fields in registers EBU_ADDRSELx.
Page 968 TC1784 LMB External Bus Unit Write ? & 2827 26 12 11 LMB Address & Equal ? Expansion Region Equal ? Selected & Equal ? Equal ? 2827 26 EBU_ADDRSELx ALTSEG MASK Register 1615 14 BASE REGENAB ALTENAB WRPROT MCA05722...
Page 969 TC1784 LMB External Bus Unit 3. The most significant four bits of the LMB address (“main” segment address) are compared to the most significant four bits of the BASE bit field. The result of the comparison (1 if equal, otherwise 0) is fed to the OR gate.
Page 970 128 Mbyte A[26:0] 1) These region size selections do not affect the external address bus of the TC1784 because A24, A25,and A26 are not output at pins (only A[21:1] are available at TC1784 pins). The EBU uses the four region select outputs from the above scheme, in conjunction with its own address decode logic, to react to LMB accesses as follows: 1.
Page 971: Access Parameter Selection
TC1784 LMB External Bus Unit 12.7.5 Access Parameter Selection Selection of the appropriate access parameters is shown in Figure 12-5: Error No Match Region 0 Access Addr. Compare Parameter Check Region 1 Region Addr. Compare Region Arbi- Latched Matched Region 2 tration Addr.
Page 972: Programming Sequence Locking
TC1784 LMB External Bus Unit The next cycle (Cycle n + 3) sees these parameters being passed to the appropriate external access cycle state machine (used to select/initialize the appropriate external access cycle, and also to select the external bus pins to be used for the access cycle).
Page 973: Address Alignment During Bus Accesses
TC1784 LMB External Bus Unit example, if the LMB requests to read a 64-bit word and the external device is only 16-bit wide, the EBU will automatically perform four external 16-bit accesses. The external accesses are performed in ascending LMB address order.
Page 974: Lmb Data Buffering
TC1784 LMB External Bus Unit 12.8 LMB Data Buffering The data for all LMB writes are “posted” into a buffer in the LMB interface before the access is passed to the state machine blocks for execution. 12.9 Standard Access Phases Accesses to asynchronous devices are composed of a number of standard access phases (according to the type of device and the type of access).
Page 975: Address Hold Phase (Ah)
TC1784 LMB External Bus Unit 12.9.2 Address Hold Phase (AH) The Address Hold Phase is optional. It consists of zero or more LMB_CLK cycles. It is intended to provide hold time for the multiplexed address bits after the ADV signal has returned to the inactive state.
Page 976: Command Delay Phase (Cd)
TC1784 LMB External Bus Unit 12.9.3 Command Delay Phase (CD) The Command Delay phase is optional. This means that it can also be programmed for a length of zero EBU_CLK clock cycles. The CD phase allows for the insertion of a delay between Address Phase (or optional Address Hold phase) and Command Phase(s).
Page 977: Data Hold Phase (Dh)
TC1784 LMB External Bus Unit • Returns the asserted CS high if the access is a read or the length of the Data Hold Phase is zero. 12.9.5 Data Hold Phase (DH) The Data Hold phase is optional. This means that it can also be programmed for a length of zero EBU_CLK clock cycles.
Page 978 TC1784 LMB External Bus Unit a region associated with CS2, the delay will be the highest of BUSRAP1.DTACS and BUSRAP1.RDRECOVC. In this case, if BUSRAP1.DTACS is greater than BUSRAP1.RDRECOVC, then the number of recovery cycles between the two accesses is BUSRAP1.DTACS clock cycles (minimum).
Page 979 TC1784 LMB External Bus Unit Table 12-14 Parameters for Recovery Phase Case Parameter(s) used to calculate “Highest Wins” Recovery Phase Region Current Next Access Access Same CSn Read Read RDRECOVC Write Write WRRECOVC Read Write BUSRAPx.DTACS, RDRECOVC Write Read BUSWAPx.DTACS, WRRECOVC,...
Page 980: Asynchronous Read/Write Accesses
TC1784 LMB External Bus Unit 12.10 Asynchronous Read/Write Accesses Asynchronous read/write access of the EBU support the following features: • EBU_CLK clock-synchronous signal generation • Support for 16-bit and Performing an LMB access with a data width greater than that of the external device automatically triggers a sequence of the appropriate number of external accesses to match the LMB access width.
Page 981: Standard Asynchronous Access Phases
TC1784 LMB External Bus Unit 12.10.2 Standard Asynchronous Access Phases Accesses to asynchronous devices are composed of a subset of the standard access phases which are detailed in Section 12.9. The standard access phases for asynchronous devices are: • AP: Address Phase (compulsory - see...
Page 982: Control Of Adv & Other Signal Delays During Asynchronous Accesses
TC1784 LMB External Bus Unit Table 12-16 Asynchronous Access Programmable Parameters (cont’d) Register Parameter Function (Bit/Bit field) EBU_BUSCONx WAIT External Wait State control (OFF, asynchronous, synchronous) WAITINV Reversed polarity at WAIT: active low or active high EBSE Control Signal Timing (for ADV)
Page 983 TC1784 LMB External Bus Unit Table 12-18 RD and RD/WR Signal Timing EXTCLOCK is set Set at: Cleared at: Delay Delay Delay Delay Disabled Enabled Disabled Enabled Start of CP1 Start of CP1 End of CPn End of CPn +...
Page 984 TC1784 LMB External Bus Unit Table 12-20 Write Data Signal Timing EXTCLOCK is set Driven at: Removed at: Delay Delay Delay Delay Disabled Enabled Disabled Enabled Start of CP1 Start of CP1 End of DHn End of DHn + , 10...
Page 985: Accesses To Multiplexed Devices
TC1784 LMB External Bus Unit 12.10.5 Accesses to Multiplexed Devices EBU_CLK CDi1 CPi1 CPi2 AD(15:0) Address data in A(MAX:16) address (a) Read Access EBU_CLK CDi1 CPi1 CPi2 AD(15:0) address data out A(MAX:16) address Figure 12-7 Multiplexed External Bus Access Cycles Figure 12-7 above shows an example of a read access to a multiplexed device.
Page 986: Interfacing To Nand Flash Devices
TC1784 LMB External Bus Unit • Address Phase (compulsory) • Address Hold Phase (optional) • Command Delay Phase (optional) • Command Phase (compulsory) • Data Hold Phase (optional) • Recovery Phase (optional) 12.10.6 Interfacing to Nand Flash Devices The memory controller provides limited support for specific Nand Flash devices. The...
Page 987 TC1784 LMB External Bus Unit The R/B input from the NAND flash is connected to the memory controller WAIT input and is available as the EBU_MODCON.STS. This enables a NAND flash to be driven by software from the processor. As shown above only two address lines are connected to the Nand Flash, and rather than being connected to address inputs, they are connected to control inputs.
Page 988 TC1784 LMB External Bus Unit a duration of one clock cycle as in this case the data hold phase is mandatory to ensure that the RD and RD/WR signals return to the high state. The command phase will be forced to have a minimum length of two clocks.
Page 989 TC1784 LMB External Bus Unit Example Nand Flash Read Sequence Figure 12-10 shows an example of how the processor can generate a Nand Flash read access sequence given this configuration:- User´s Manual 12-39 V1.1, 2011-05 EBUT13L-A, V1.16...
Page 990 TC1784 LMB External Bus Unit Figure 12-10 Example of an Memory Controller Nand Flash access sequence (read) User´s Manual 12-40 V1.1, 2011-05 EBUT13L-A, V1.16...
Page 991: Dynamic Command Delay And Wait State Insertion
TC1784 LMB External Bus Unit 1. In the cycle marked ‘1’ in Figure 12-10 the processor initiates a read sequence by writing the “Read Command” value to address “NAND_FLASH_BASE + 0x40000”. This generates a write sequence with CLE (A(17)) driven high and ALE (A(16)) driven low.
Page 992 TC1784 LMB External Bus Unit rising edge of EBU_CLK to decide whether to prolong the Command Phase or to start the next phase. Figure 12-11 shows an example of WAIT used in Synchronous Mode. Note: Due to the one-cycle delay in Synchronous Mode between the sampling of the WAIT input and its evaluation by the EBU, the Command Phase must always be programmed to be at least one EBU_CLK cycle (via EBU_BUSAPx.WAITRDC or...
Page 993 TC1784 LMB External Bus Unit EBU_CLK CPi1 CPi2 CPe3 A[23:0] Address AD[15:0] Address Data in WAIT (active low) In the example above, the Command Delay phase is internally Note: programmed to zero EBU_CLK cycles (no Command Delay phase). The Command Phase is internally programmed to one EBU_CLK cycle.
Page 994 TC1784 LMB External Bus Unit • Finally at EBU_CLK edge 5, as a result of the WAIT input sampled as high at EBU_CLK edge 3, the EBU terminates the Command Phase, reads the input data from AD[15:0],and starts the Recovery Phase.
Page 995: Ebu Registers
TC1784 LMB External Bus Unit 12.11 EBU Registers This section describes the registers and programmable parameters of the EBU. All these registers can be read in User Mode, but can only be written in Supervisor Mode. All registers are reset by the module reset.
Page 996 TC1784 LMB External Bus Unit Table 12-23 Registers OverviewEBU Control Registers Register Register Long Offset Access Mode Description Short Name Name Address Read Write EBU_BUSRCON0 EBU Bus Read 0028 U, SV, SV, 32, Page 12-54 Configuration Register 0 EBU_BUSRAP0 EBU Bus Read...
Page 997 TC1784 LMB External Bus Unit Table 12-23 Registers OverviewEBU Control Registers Register Register Long Offset Access Mode Description Short Name Name Address Read Write EBU_BUSWAP2 EBU Bus Write 0054 U, SV, SV, 32, Page 12-62 Access Parameter Register 2 EBU_BUSRCON3 EBU Bus Read...
Page 998: Clock Control Register, Clc
TC1784 LMB External Bus Unit 12.11.1 Clock Control Register, CLC EBU_CLC EBU Clock Control Register (0000 Reset Value: 0011 0000 EBUDIVA SYNC EBUDIV SYNC DISS DISR Field Bits Type Description DISR EBU Disable Request Bit This bit is used for enable/disable control of the EBU.
Page 999: Configuration Register, Modcon
TC1784 LMB External Bus Unit Field Bits Type Description EBUDIV 19:18 EBU Clock Divide Ratio request EBU to run off input clock (default after reset) request EBU to run off input clock divided by 2 request EBU to run off input clock divided by 3...
Page 1000 TC1784 LMB External Bus Unit Field Bits Type Description Memory Status Bit Software access to the WAIT input pin to the EBU. LCKABRT Lock Abort This is a status bit which is set when a chip select lock has been cancelled by a program fetch. The flag is cleared by writing 1 to the field.