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19.1.3
Upstream Channel
The MSC upstream channel is an asynchronous serial receiver based on the standard
asynchronous data transfer protocol. It is dedicated to receive a serial data stream from
a peripheral device via its serial data input SDI, using two specific data frame formats.
Figure 19-14
is a block diagram of the MSC upstream channel.
f
MSC
Figure 19-14 Upstream Channel Block Diagram
The incoming data at SI is sampled after it has been filtered for spikes. The detected
logic states of the serial input are clocked into a shift register. After the complete
reception of the serial data frame, the content of the shift register is transferred into one
of the four data registers, and an interrupt can be generated optionally.
The reception baud rate is directly coupled to the module clock
a range of
f
/4 up to
MSC
User's Manual
MSC, V1.37 2009-05
Upstream
Channel
Control
Serial Receive Buffer
Shift Register
Upstream Data Registers
UD0
UD1
UD2
UD3
f
/256.
MSC
19-21
Micro Second Channel (MSC)
RDI
Input Control
Spike
Samp-
SI
Filter
ling
f
TC1728
Interrupt
M
SDI
U
SDI[7:0]
X
MCB06240
, and can be within
MSC
V1.0, 2011-12
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