Control Registers - Infineon Technologies TC1728 User Manual

Field Bits
0 [31:16] r
Note: Implementation specific details (e.g. reset value) see
Registers" on Page
18.2.2

Control Registers

The PISEL register controls the input signal selection of the SSC module. Each input of
the module kernel receive, transmit and clock signals has associated two input lines
(marked by suffix A and B).
PISEL
Port Input Select Register
31 30 29 28
15 14 13 12
Field Bits
MRIS 0
SRIS 1
SCIS 2
User's Manual
SSC, V1.41 2010-06
Type Description
Reserved
Read as 0.
18-43.
27 26 25
11 10 9
0
r
Type Description
rw Master Mode Receive Input Select
MRIS selects the receive input line in Master Mode.
0
B
1
B
rw Slave Mode Receive Input Select
SRIS selects receive input line in Slave Mode.
0
B
1
B
rw Slave Mode Clock Input Select
SCIS selects the module kernel SCLK input line that is
used as clock input line in slave mode.
0
B
1
B
Synchronous Serial Interface (SSC)
(04 )
H
24 23 22 21
0
r
8 7 6
STIP 0
rw r
Receive input line MRSTA is selected
Receive input line MRSTB is selected
Receive input line MTSRA is selected
Receive input line MTSRB is selected
Slave Mode clock input line SCLKA is selected
Slave Mode clock input line SCLKB is selected
18-29
"Module Identification
Reset Value: 0000 0000
20 19 18
5 4 3 2
SLSIS SCIS SRIS
rw rw
V1.0, 2011-12
TC1728
H
17 16
1 0
MRI
S
rw rw