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16.2.2
PCP OCDS Level 1
PCP has no hardware means of generating trigger events.
To set breakpoints, the debugger is expected to patch the code in the PCP code memory
(CMEM) with DEBUG instructions. If a DEBUG instruction is executed, the running
channel program is terminated, either with Debug Exit or with Error Exit.
The PCP has a suspend input, a break input and a break output. The Break Switch can
send an external break request to the PCP, with the same consequence as above
(Debug Exit or Error Exit).
16.2.3
SBCU OCDS Level 1
The BCU of the SPB bus in the TC1728 offers very powerful means for trigger
generation. The BCU contains comparators for
•
the arbitration phase (look for specific bus master)
•
the address phase (look for specific address or range)
•
the data phase (look for read, write, supervisor mode, etc.)
The results can be combined to generate a break request signal, which is sent to the
Break Switch.
The OCDS registers of SBCU are described in chapter "On-Chip System Buses and Bus
Bridges" starting from section "System Bus Control Unit Registers".
16.2.4
DMA OCDS Level 1
The DMA controller in the TC1728 provides the following debugging capabilities:
•
Hard suspend mode of the DMA controller (for test purposes only)
•
Soft suspend mode of DMA channels
•
Break signal generation
In suspend modes, the operations of DMA channels or the complete module are
stopped. Under certain conditions, a break signal is also generated for the on-chip debug
support logic.
More details on the OCDS Level 1 debug capabilities of the DMA controller are provided
in section "On-Chip Debug Capabilities" of the DMA chapter.
User's Manual
OCDS, V1.5
On-Chip Debug Support (OCDS)
16-9
TC1728
V1.0, 2011-12
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