Infineon Technologies TC1728 User Manual page 1197

Field Bits
INACT [5:4]
SLSO7MOD 8
QSMEN 14
EN 15
0 [7:6],
[13:9],
[31:16]
1) For getting a best case timing with no timing delays (see
the SLSOn outputs are disabled (SSOC.OENn bits set to 0).
Note: The SSOTC register timing parameters LEAD, TRAIL, INACT, and SLSO7MOD
are latched by each TB register write operation and remain latched during a
consecutive serial transmission. Bits QSMEN and EN of register SSOTC are not
latched.
User's Manual
SSC, V1.41 2010-06
Type Description
rw Slave Output Select Inactive Delay
This bit field determines the number of inactive delay
clock cycles. An inactive delay clock cycle is always a
multiple of an SCLK shift clock period.
00 Zero inactive delay clock cycle selected
B
01 One inactive delay clock cycle selected
B
10 Two inactive delay clock cycles selected
B
11 Three inactive delay clock cycles selected
B
rw SLSO7 Delayed Mode Selection
This bit selects the delayed mode for the SLSO7
slave select output.
0 Normal mode selected for SLSO7
B
1 Delayed mode selected for SLSO7
B
w Queued SSC Mode Enabled
0 When QSMEN is written with 0, the state of bit
B
SSOTC.EN is don't care. In this case, the
enable/disable of the SSC is controlled by bit
CON.EN only. Note that EN should only be
cleared by software while no transfer is in
progress (STAT.BSY = 0).
1 When QSMEN is written with 1, queued SSC
B
mode is enabled, and the state of bit
SSOTC.EN is copied to CON.EN.
QSMEN is always read as 0.
rw Enable Bit
0 Transmission and reception are disabled.
B
1 Transmission and reception are enabled.
B
Note that the transmission/reception enable can also
be controlled in queued SSC mode by bit CON.EN.
r Reserved
Read as 0; should be written with 0.
18-40
Synchronous Serial Interface (SSC)
Figure 18-9), this bit field value should be set when
TC1728
1)
V1.0, 2011-12