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13.3.1.2 Operation of the Interrupt Control Unit (ICU)
Service-request arbitration is performed in the ICU in parallel with normal CPU
operation. When a triggering event occurs in one or more interrupt sources, the
associated SRNs, if enabled, send service requests to the CPU through the ICU. The
ICU determines which service request has the highest priority. The ICU will then forward
the service request to the CPU. The service request will be acknowledged by the CPU
and serviced, depending upon the state of the CPU.
The ICU arbitration process takes place in one or more arbitration cycles over the CPU
interrupt arbitration bus. The ICU begins a new arbitration process when a new service
request is detected. At the end of the arbitration process, the ICU will have determined
the service request with the highest priority number. This number is stored in the
ICR.PIPN bit field and becomes the pending service request.
After the arbitration process, the ICU forwards the pending service request to the CPU
by attempting to interrupt it. The CPU can be interrupted only if interrupts are enabled
globally (that is, ICR.IE = 1) and if the priority of the service request is higher than the
current processor priority (ICR.PIPN > ICR.CCPN). Also, the CPU may be temporarily
blocked from taking interrupts, for example, if it is executing a multi-cycle instruction such
as an atomic read-modify-write operation. The full list of conditions which could block the
CPU from immediately responding to an interrupt request generated by the ICU is:
•
Current CPU priority, ICR.CCPN, is equal to or higher than the pending interrupt
priority, ICR.PIPN
•
Interrupt system is globally disabled (ICR.IE = 0)
•
CPU is in the process of entering an interrupt- or trap-service routine
•
CPU is executing non-interruptible trap services
•
CPU is executing a multi-cycle instruction
•
CPU is executing an instruction which modifies the conditions of the global interrupt
system, such as modifying the ICR
•
CPU detects a trap condition (such as context depletion) when trying to enter a
service routine
When the CPU is not otherwise prevented from taking an interrupt, the CPU's program
counter will be directed to the Interrupt Service Routine entry point associated with the
priority of the service request. Next, the CPU saves the value of ICR.PIPN internally, and
acknowledges the ICU. The ICU then forwards the acknowledge signal back to the SRN
that is requesting service in order to inform it that it will be serviced by the CPU. The SRR
bit in this SRN is then reset to 0.
After sending the acknowledgement, the ICU resets ICR.PIPN to 0 and may start a new
arbitration process if there is another pending interrupt request. If not, ICR.PIPN remains
at 0 and the ICU enters an idle state, waiting for the next interrupt request to awaken it.
If there is a new service request waiting, the priority number of the new request will be
written to ICR.PIPN at the end of the new arbitration process and the ICU will deliver the
pending interrupt to the CPU according to the rules described in this section.
User's Manual
Interrupt, V1.4
13-10
TC1728
Interrupt System
V1.0, 2011-12
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