Error Detection Mechanisms - Infineon Technologies TC1728 User Manual

18.1.2.10 Error Detection Mechanisms

The SSC is able to detect four different error conditions. Receive Error and Phase Error
are detected in all modes, while Transmit Error and Baud Rate Error apply to Slave Mode
only. In case of a Transmit Error or Receive Error, the respective error flags are always
set and the error interrupt requests will be generated by activating the EIR line only if the
corresponding error enable bits have been set (see
handler may then check the error flags to determine the cause of the error interrupt. The
error flags are not cleared automatically, but must be cleared via register EFM after
servicing. This allows servicing of some error conditions via interrupt, while others may
be polled by software. The error status flags can be set and cleared by software via the
error flag modification register EFM.
Note: The error interrupt handler must clear the associated (enabled) error flag(s) to
prevent repeated interrupt requests. The setting of an error flag by software does
not generate an interrupt request.
User's Manual
SSC, V1.41 2010-06
Synchronous Serial Interface (SSC)
Figure
18-20
TC1728
18-12). The error interrupt
V1.0, 2011-12