Infineon Technologies TC1728 User Manual page 1209

Field Bits
0 [31:6]
Note: After a hardware reset operation, the
the SSC modules are disabled (DISS set).
Fractional Divider Register
Each SSC has its own fractional divider register. The Fractional Divider Registers
SSCx_FDR control the clock rate of the shift clocks
SSC0_FDR
SSC0 Fractional Divider Register
SSC1_FDR
SSC1 Fractional Divider Register
SSC2_FDR
SSC2 Fractional Divider Register
SSC3_FDR
SSC3 Fractional Divider Register
31 30 29 28
DIS EN SUS SUS
CLK HW REQ ACK
rwh rw rh rh
15 14 13 12
DM SC
rw rw
Field Bits
STEP [9:0]
SM 11
SC [13:12]
User's Manual
SSC, V1.41 2010-06
Type Description
r Reserved
Read as 0; should be written with 0.
(0C
(0C
(0C
(0C
27 26 25 24
0
r rh
11 10 9 8
SM 0
rw rw
Type Description
rw Step Value
Reload or addition value for RESULT.
rw Suspend Mode
SM selects between granted or immediate suspend
mode.
rw Suspend Control
This bit field determines the behavior of the fractional
divider in suspend mode.
18-52
Synchronous Serial Interface (SSC)
f
clocks are disabled, and therefore also
CLCx
f
.
SSCx
) Reset Value: 1000 0000
H
) Reset Value: 1000 0000
H
) Reset Value: 1000 0000
H
) Reset Value: 1000 0000
H
23 22 21 20
RESULT
7 6 5
STEP
rw
TC1728
19 18 17
4 3 2 1
V1.0, 2011-12
H
H
H
H
16
0