Stm Module Implementation; On-Chip Service Request Connections; Stm Address Map - Infineon Technologies TC1728 User Manual

14.4

STM Module Implementation

This section defines implementation specific details of the STM in the TC1728.
14.4.1

On-chip Service Request Connections

The two compare match service request outputs STMIR0 and STMIR1 are connected in
the TC1728 to on-chip devices as described in
Table 14-4 System Timer On-Chip Interconnections
Service Request Signal
STMIR0
STMIR1
14.4.2

STM Address Map

Table 14-5 defines the complete address range of the STM with absolute addresses and
the read/write access rights.
Table 14-5 Address Map of STM
Short Name Description
System Timer (STM)
STM_CLC STM Clock Control
Register
– Reserved
STM_ID STM Module Identification
Register
– Reserved
STM_TIM0 STM Timer Register 0
STM_TIM1 STM Timer Register 1
User's Manual
STM, V1.6
Table 14-4.
Connected to
DMA Channel 00 Request Input 8
DMA Channel 01 Request Input 8
DMA Channel 02 Request Input 8
DMA Channel 03 Request Input 8
DMA Channel 04 Request Input 8
DMA Channel 05 Request Input 8
DMA Channel 06 Request Input 8
DMA Channel 07 Request Input 8
ADC0_REQGT[4:0]_5
ADC1_REQGT[4:0]_5
Address Access Mode Reset Value
Read
F000 0200 U, SV SV, E 0000 0200
H
F000 0204 BE
H
F000 0208 U, SV BE
H
F000 020C BE
H
F000 0210 U, SV U, SV 0000 0000
H
F000 0214 U, SV U, SV 0000 0000
H
14-21
TC1728
System Timer (STM)
Write
BE –
0000 C0XX
BE –
V1.0, 2011-12
H
H
H
H