Multican Kernel Functional Description; Module Structure - Infineon Technologies TC1728 User Manual

20.3

MultiCAN Kernel Functional Description

This section describes the functionality of the MultiCAN module.
20.3.1

Module Structure

Figure 20-6 shows the general structure of the MultiCAN module.
CAN Bus 0 CAN Bus 1
CAN
Node 0
Interrupt
Control
Logic
interrupt control
Figure 20-6 MultiCAN Block Diagram
CAN Nodes
Each CAN node consists of several sub-units.
• Bitstream Processor
The Bitstream Processor performs data, remote, error and overload frame
processing according to the ISO 11898 standard. This includes conversion between
the serial data stream and the input/output registers.
• Bit Timing Unit
The Bit Timing Unit determines the length of a bit time and the location of the sample
point according to the user settings, taking into account propagation delays and
phase shift errors. The Bit Timing Unit also performs resynchronization.
User's Manual
MultiCAN, V2.24
Controller Area Network Controller (MultiCAN)
. . .
CAN
. . .
Node 1
Message Controller
Message
RAM
Address Decoder
bus interface
CAN Bus x-1
CAN
Node x-1
List
Control
Logic
20-14
TC1728
Node Bitstream
Processor
Control
Unit
Bit Error
Timing Handling
Frame
Unit Unit
Counter
Interrupt Control Unit
MultiCAN_Blockdiag_x.vsd
V1.0, 2011-12