Clock Control Register - Infineon Technologies TC1728 User Manual

17.3.2.1 Clock Control Register

The Clock Control Register ASC0_CLC allows the programmer to adapt the functionality
and power consumption of the ASC modules to the requirements of the application. The
description below shows the clock control register functionality which is implemented for
the ASC modules. Because ASC0 and ASC1 share one common clock control interface,
ASC0_CLC controls the
shut-off mode for both modules.
ASC0_CLC
ASC0 Clock Control Register
31 30 29 28
15 14 13 12
Field Bits
DISR 0
DISS 1
SPEN 2
EDIS 3
SBWE 4
FSOE 5
RMC [15:8]
0 [7:6],
[31:16]
User's Manual
ASC, V1.3 2007-11
Asynchronous/Synchronous Serial Interface (ASC)
f module clock signal, sleep mode, suspend mode and fast
ASC
27 26 25
11 10 9
RMC
rw
Type Description
rw Module Disable Request Bit
Used for enable/disable control of the module.
r Module Disable Status Bit
Bit indicates the current status of the module.
rw Module Suspend Enable for OCDS
Used to enable the suspend mode.
rw Sleep Mode Enable Control
Used to control module's sleep mode.
w Module Suspend Bit Write Enable for OCDS
Determines whether SPEN and FSOE are write-
protected.
rw Fast Switch Off Enable
Used to switch off fast clock in Suspend Mode.
rw 8-bit Clock Divider Value in RUN Mode
r Reserved
Read as 0; should be written with 0.
(00 )
H
24 23 22 21
0
r
8 7 6 5
FS
0
OE
r rw
17-35
TC1728
Reset Value: 0000 0003
20 19 18 17
4 3 2 1
SB E SP DIS
WE DIS EN S
w rw rw r
V1.0, 2011-12
H
16
0
DIS
R
rw