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At the MSC downstream channel, the internal serial clock output FCL and data output
line SO are available outside the MSC module as two signal pairs with inverted signal
polarity, FCLP/FCLN and SOP/SON. Both, clock and data outputs, are generated from
the module internal signals FCL and SO according to
Figure 19-21 Downstream Channel: Clock and Data Output Control
With OCR.CLP = 0, FCLP has identical and FCLN has inverted polarity compared to
FCL. Setting OCR.CLP, exchanges the signal polarities of FCLP and FCLN. An
equivalent control capability is available for the SOP and SON data outputs (controlled
by OCR.SLP).
One additional control capability not shown in
signal. With OCR.CLKCTRL = 1, the FCL clock signal will always be generated,
independently whether a downstream frame is currently transmitted or not. If
OCR.CLKCTRL = 0, FCL becomes only active during the active phases of data or
command frames (not during passive time frames).
User's Manual
MSC, V1.37 2009-05
OCR
FCL
SO
19-29
Micro Second Channel (MSC)
Figure
CLP
SLP
0
FCLP
1
0
FCLN
1
0
SOP
1
0
SON
1
MCA06247
Figure 19-21
TC1728
19-21.
is available for the FCL
V1.0, 2011-12
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