Infineon Technologies TC1728 User Manual page 1175

INACT, and SLSO7MOD) and register SSOC (AOLn and OENn) are latched and remain
valid for the consecutive transmission. Following that, SLSOn becomes active (low) for
a number of SCLK cycles (leading delay cycles) before the first bit of the serial data
stream occurs at MTSR. After the transmission of the data frame, SLSOn remains active
(low) for a number of SCLK cycles (trailing delay cycles) before it becomes inactive
again. This inactive state of SLSOn is valid at least for a number of SCLK cycles (inactive
delay cycles) before a new chip select period can be started.
Note: When operating in Master Mode with CON.PH = 1 and sampling data from a slave
device that becomes enabled by an SLSOn output, a leading delay of at least one
leading delay clock cycle should be selected. The reason is that with CON.PH = 1,
the first SCLK edge already latches the first data bit at MRST.
The three parameters of a chip select period are controlled by bit fields in the Slave
Select Output Timing Control Register SSOTC. Each of these bit fields can contain a
value from 0 to 3 defining delay cycles of 0 to 3 multiples of the
The three parameters are:
1. Number of leading delay cycles (
2. Number of trailing delay cycles (
3. Number of inactive delay cycles (
If SSOTC.INACT = 00
next data frame, the next chip select period is started with its leading delay phase without
SLSOn going inactive. If, in this case, TB has not been loaded in time with the data for
the next data frame, SLSOn becomes inactive again.
Slave Select Output Control
Each slave select output SLSOn can be enabled individually. When SSOC.OENn = 1,
SLSOn is enabled. Furthermore, active and inactive levels of the SLSOn outputs are
programmable. Bit SSOC.AOLn determines the state of the active level of SLSOn.
Slave Select
Output
Timing Control
SSOTC
Figure 18-10 Slave Select Output Control Logic
User's Manual
SSC, V1.41 2010-06
t
SLSOL
t
SLSOT
t
SLSOI
and register TB has already been loaded with the data for the
B
Slave Select Output Generation Unit
SSOC.OENn
1
0: inactive
1: active
0
0
Synchronous Serial Interface (SSC)
= SSOTC.LEAD ×
= SSOTC.TRAIL ×
= SSOTC.INACT ×
SSOC.AOLn
n = 0-7
1
0
18-18
TC1728
t
shift clock period.
SCLK
t
)
SCLK
t
)
SCLK
t
)
SCLK
SLSOANDIn
&
SLSOANDOn
SLSOn
MCA06221_mod
V1.0, 2011-12