Port Input Register - Infineon Technologies TC1728 User Manual

Field Bits
ENx x
(x = 0-15)
0 [31:16] r
Note: Ports 0 and 5 are 16-bit wide ports entirely used by the GPTA modules. The
Pn_ESR registers of the other ports have a reduced number of bits (see Pn_ESR
register descriptions in the corresponding port sections).
9.3.7

Port Input Register

The logic level of a GPIO pin can be read via the read-only port input register Pn_IN.
Reading the Pn_IN register allways returns the current logical value at the GPIO pin
independently whether the pin is selected as input or output.
Pn_IN (n=0-6)
Port n Input Register
Pn_IN (n=8-11)
Port n Input Register
P12_IN
Port 12 Input Register
31 30 29 28
15 14 13 12
P15 P14 P13 P12 P11 P10
rh rh rh rh
User's Manual
Ports, V2.0
General Purpose I/O Ports and Peripheral I/O Lines (Ports)
Type Description
rw Emergency Stop Enable for Port n Pin x
This bit enables the emergency stop function for
GPIO lines used as GPTA outputs. If the emergency
stop condition is met and enabled, the output
selection is automatically switched from alternate
(GPTA output) function to GPIO output function.
0 Emergency stop function for Pn.x is disabled.
B
1 Emergency stop function for Pn.x is enabled.
B
Reserved
Read as 0; should be written with 0.
(F000 0C24
(F000 0C24
(24
27 26 25 24
11 10 9 8
P9 P8
rh rh rh rh
9-23
+ n*100 ) Reset Value: 0000 XXXX
H H
+ n*100 ) Reset Value: 0000 XXXX
H H
) Reset Value: 0000 XXXX
H
23 22 21
0
r
7 6 5
P7 P6 P5 P4
rh rh rh
TC1728
20 19 18 17
4 3 2 1
P3 P2 P1
rh rh rh rh
V1.0, 2011-12
H
H
H
16
0
P0
rh