Infineon Technologies TC1728 User Manual page 1178

Transmit Error
EFM.SETTE
EFM.CLRTE
Receive Error
EFM.SETRE
EFM.CLRRE
Phase Error
EFM.SETPE
EFM.CLRPE
Baud Rate Error
EFM.SETBE
EFM.CLRBE
Parity Error
EFM.SETPARE
EFM.CLRPARE
Figure 18-12 SSC Error Interrupt Control
A Receive Error (Master or Slave mode) is detected when a new data frame is
completely received, but the previous data was not read out of the receive buffer register
RB. If enabled via CON.REN, this condition sets the error flag STAT.RE and activates
the error interrupt request line EIR. This condition sets the error flag STAT.RE and, if
enabled via CON.REN, sets the error interrupt request line EIR. The old data in the
receive buffer RB will be overwritten with the new value and is irretrievably lost.
A Phase Error (Master or Slave Mode) is detected when the incoming data at pin MRST
(Master Mode) or MTSR (Slave Mode), sampled with the same frequency as the module
User's Manual
SSC, V1.41 2010-06
&
CON.TEN
Set
Clear
&
CON.REN
Set
Clear
&
CON.PEN
Set
Set
Clear
&
CON.BEN
Set
Set
Clear
CON.
&
PAREEN
Set
Set
Clear
Synchronous Serial Interface (SSC)
Set
STAT.TE
Set
STAT.RE
STAT.PE
STAT.BE
STAT.PARE
18-21
TC1728
≥1
Error
Interrupt
EIR
MCA05789a_mod_ist
V1.0, 2011-12