Infineon Technologies XC800 User Manual
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Infineon Technologies XC800 User Manual

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User's Manual, V 0.1, Jan 2005
XC800
M i c r o c o n t r o l l e r F a m i l y
A r c h i t e c t u r e a n d I n s t r u c t i o n S e t
M i c r o c o n t r o l l e r s
N e v e r
s t o p
t h i n k i n g .

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  • Page 1 User’s Manual, V 0.1, Jan 2005 XC800 M i c r o c o n t r o l l e r F a m i l y A r c h i t e c t u r e a n d I n s t r u c t i o n S e t...
  • Page 2 Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life.
  • Page 3 User’s Manual, V 0.1, Jan 2005 XC800 M i c r o c o n t r o l l e r F a m i l y A r c h i t e c t u r e a n d I n s t r u c t i o n S e t...
  • Page 4 XC800 Revision History: 2005-01 V 0.1 Previous Version: Page Subjects (major changes since last revision) We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document.

  • Page 5: Table Of Contents

    XC800 XC800 Table of Contents Page Fundamental Structure ........1 Foreword .
  • Page 6 XC800 Table of Contents Page Instruction Set ..........1 Addressing Modes .

  • Page 7: Fundamental Structure

    This manual provides an overview of the architecture and functional characteristics of the XC800 microcontroller family. It also includes a complete description of the XC800 core instruction set. For detailed information on the different derivatives of the XC800 8- bit microcontrollers, refer to the respective user’s manuals.

  • Page 8: Memory Organization

    Fundamental Structure Memory Organization The memory partitioning of the XC800 microcontrollers is typical of the Harvard architecture where data and program areas are held in separate memory space. The on-chip peripheral units are accessed using an internal Special Function Register (SFR) memory area that occupies 128 bytes of address, which can be mapped or paged to increase the number of addressable SFRs.

  • Page 9: Memory Extension

    The standard amount of addressable program or external data memory in an 8051 system is 64 Kbytes. The XC800 core supports memory expansion of up to 1 Mbyte and this is enabled by the availability of a Memory Management Unit (MMU) and a Memory Extension Stack.
  • Page 10 XC800 Fundamental Structure Relative jumps (SJMP etc.) and absolute jumps within 2-Kbyte regions (AJMPs), however, will in no way change the current bank. In other words, these instructions do not deselect the active 64-Kbyte bank block. Move Constant Instructions (MOVC) MOVC instructions access data bytes in either the Current bank (CB19 –...

  • Page 11: Program Memory

    EA pin. Most XC800 derivatives include a section for Boot ROM code, the size of which depends on the derivative. Usually, the Boot ROM code is executed first after reset where the Boot ROM is mapped starting from base address 0000 of the code space.

  • Page 12: Internal Data Memory Xram

    1.3.3.2 Internal Data Memory XRAM The size of the internal XRAM is not fixed and varies depending on XC800 derivative. The internal XRAM is mapped to both the external data space and the code space because it can be accessed using both ‘MOVX’ and ‘MOVC’ instructions. When accessed using the 8-bit MOVX instruction via register R0 or R1, the SFR XADDRH must be initialized to specify the upper address byte.

  • Page 13: Special Function Register Extension By Mapping

    XC800 Fundamental Structure The Special Function Registers (SFRs) are mapped to the internal data space in the range 80 to FF . The SFRs are accessible through direct addressing. The SFRs that are located at addresses with address bit 0-2 equal to 0 (addresses 80...

  • Page 14: Special Function Register Extension By Paging

    XC800 Fundamental Structure 1.3.4.2 Special Function Register Extension by Paging The number of SFRs may be further extended for some on-chip peripherals at the module level via a paging scheme. These peripherals have a built-in local SFR extension mechanism for increasing the number of addressable SFRs. The control is via bit field PAGE in the module page register MOD_PAGE.
  • Page 15 XC800 Fundamental Structure storage register should be used in parallel with the new page value, a single write operation can: • Save the contents of PAGE in STx before overwriting with the new value (this is done in the beginning of the interrupt routine to save the current page setting and program the new page number);...
  • Page 16 XC800 Fundamental Structure Field Bits Type Description PAGE [2:0] Page Bits When written, the value indicates the new page. When read, the value indicates the currently active page. STNR [5:4] Storage Number This number indicates which storage bit field is the target of the operation defined by bit field OP.

  • Page 17: Bit Protection Scheme

    32 CCLKs if the “close access” password is not written. If “open access” password is written again before the end of 32 CCLK cycles, there will be a recount of 32 CCLK cycles. The bits or bit fields that are protected may differ for the XC800 derivatives. PASSWD Password Register...

  • Page 18: Cpu Architecture

    The units represented by dotted boxes may not be available, depending on the derivative; these include peripheral units and external memory bus. Memory sizes vary depending on the XC800 microcontroller derivative. Internal Bus...
  • Page 19 Controller Non-Maskable Interrupt Figure 2-2 XC800 Core Block Diagram The arithmetic section of the processor performs extensive data manipulation and consists of the arithmetic/logic unit (ALU), A register, B register, and PSW register. The ALU accepts 8-bit data words from one or two sources, and generates an 8-bit result under the control of the instruction decoder.
  • Page 20 XC800 CPU Architecture the next instruction to be executed. The conditional branch logic enables internal and external events to the processor to cause a change in the program execution sequence. The access control unit is responsible for the selection of the on-chip memory resources.

  • Page 21: Cpu Register Description

    Selection of the active data pointer is done via the SFR EO (see Section 2.1.6). The number of data pointers available is specific to the XC800 derivative. 2.1.3 Accumulator (ACC) This register is an operand for most ALU operations. ACC is the symbol for the accumulator register.

  • Page 22: Program Status Word

    XC800 CPU Architecture 2.1.5 Program Status Word The Program Status Word (PSW) contains several status bits that reflect the current state of the CPU. Program Status Word Register Reset Value: 00 Field Bits Type Description Parity Flag Set/cleared by hardware after each instruction to indicate an odd/even number of “one”...

  • Page 23: Extended Operation Register (Eo)

    XC800 CPU Architecture 2.1.6 Extended Operation Register (EO) The EO register has two functions. One function is to select the active data pointer where the derivative has multiple data pointers. The other function is to select the instruction executed opcode...

  • Page 24: Memory Extension Registers

    XC800 CPU Architecture 2.1.7 Memory Extension Registers These registers support the memory extension feature, which may not be available on certain XC800 microcontroller derivatives. MEX1 Memory Extension Register 1 Reset Value: 00 CB[19:16] NB[19:16] Field Bits Type Description NB[19:16] [3:0]...
  • Page 25 XC800 CPU Architecture MEX3 Memory Extension Register 3 Reset Value: 00 MCB19 MX19 MX[18:16] Field Bits Type Description MX[19:16] [2:0], XRAM Bank Number XRAM Bank Selector MOVX access data in the current bank MOVX access data in the Memory XRAM...

  • Page 26: Power Control Register (Pcon)

    2.1.8 Power Control Register (PCON) The XC800 CPU has two power saving modes: idle mode and power-down mode. In idle mode, the clock to the CPU is disabled while other peripherals may continue to run (possibly at lower frequency). In power-down mode, the clock to the entire CPU is stopped.

  • Page 27: Uart Registers

    XC800 CPU Architecture 2.1.9 UART Registers The UART uses two SFRs, SCON and SBUF. SCON is the control register, while SBUF is the data register. The serial port control and status register is the SFR SCON. This register contains not only the mode selection bits, but also the 9th data bit for transmit and receive (TB8 and RB8), and the serial port interrupt bits (TI and RI).
  • Page 28 XC800 CPU Architecture Field Bits Type Description Serial Port Receiver Bit 9 In modes 2 and 3, this is the 9th data bit received. In mode 1, if SM2 = 0, this is the stop bit received. In mode 0, RB8 is not used.

  • Page 29: Timer/Counter Registers

    2.1.10 Timer/Counter Registers Two 16-bit timers, Timer 0 and Timer 1, are available in the XC800 core. The SFR TCON controls the running of the timers and generating of interrupts, while SFR TMOD sets the operating modes of the timers. The timer/counter values are stored in two pairs of 8-bit registers: TL0, TH0 and TL1, TH1.
  • Page 30 XC800 CPU Architecture TMOD Timer Mode Register Reset Value: 00 GATE1 GATE0 Field Bits Type Description T0M[1:0], [1:0], Mode select bits T1M[1:0] [5:4] T0M/T1M Function [1:0] 13-bit timer THx operates as 8-bit timer/counter TLx is a 5-bit prescaler 16-bit timer...

  • Page 31: Interrupt Registers

    XC800 CPU Architecture 2.1.11 Interrupt Registers Each interrupt for a peripheral (if available for the derivative) can be individually enabled or disabled by setting or clearing the corresponding bit in the bitaddressable interrupt enable registers IEN0 and IEN1. Register IEN0 also contains the global enable/disable bit (EA), which can be cleared to disable all interrupts at once.
  • Page 32 XC800 CPU Architecture Field Bits Type Description Enable/disable All Interrupts No interrupt will be acknowledged. Each interrupt source is individually enabled or disabled by setting or clearing its enable bit. Reserved Returns 0 if read; should be written with 0.
  • Page 33 XC800 CPU Architecture Interrupt Priority High Register Reset Value: XX00 0000 PT2H PT1H PX1H PT0H PX0H Field Bits Type Description PX0, Priority Level for External Interrupt 0 PX0H PT0, Priority Level for Timer 0 Overflow Interrupt PT0H PX1, Priority Level for External Interrupt 1...
  • Page 34 XC800 CPU Architecture Four bits are available in TCON to control and flag the external interrupts. TCON Timer Control Register Reset Value: 00 The functions of the shaded bits are not described here Field Bits Type Description External Interrupt 0 Level/Edge Trigger Control...

  • Page 35: On-Chip Debug Support Concept

    • A Monitor Mode Control (MMC) block at the center of the OCDS system brings together control signals and supports the overall functionality • MMC communicates with the XC800 core primarily via the Debug Interface, and also receives reset and clock signals •...
  • Page 36 XC800 CPU Architecture • Two interfaces can be used to access the OCDS system: – JTAG as a primary channel; dedicated exclusively to test and debug activities and is not normally used in an application – UART as an alternative channel; it has the advantage of needing fewer pins, but causes a loss (at least partially) to the standard serial interface while debugging •...

  • Page 37: Basic Interrupt Handling

    2.3.1 Interrupt Source and Vector Address Each interrupt source has an associated interrupt vector address. This vector is accessed to service the corresponding interrupt source. The assignment of the XC800 interrupt sources is summarized in Table 2-2.The extended interrupts are generally assigned to on-chip peripherals, which vary depending on the XC800 derivative.

  • Page 38: Interrupt Response Time

    XC800 CPU Architecture 3. The instruction in progress is RETI or any write access to registers IEN0/IEN1 or IP,IPH/IP1,IP1H. Any of these three conditions will block the generation of the LCALL to the interrupt service routine. Condition 2 ensures that the instruction in progress is completed before vectoring to any service routine.

  • Page 39: Service Order

    Thus, within each priority level there is a second priority structure determined by the polling sequence as shown in Table 2-3. The extended interrupts that are applicable, vary depending on the XC800 derivative. Table 2-3 Priority Structure within Interrupt Level Source...
  • Page 40 XC800 CPU Architecture Table 2-3 Priority Structure within Interrupt Level (cont’d) Source Level Extended Interrupt 12 Extended Interrupt 13 User’s Manual, V 0.1 2-23 2005-01...

  • Page 41: Cpu Timing

    P2 of the last machine cycle for the current instruction. The XC800 core supports access to slow (internal) memory by using wait state(s). Each wait state lasts one machine cycle. For example, in case of a memory requiring one wait state, the access time is increased by one machine cycle after every byte of opcode/ operand fetched.
  • Page 42 • fetching the operand/s (for instructions > 1 byte) • fetching the first byte (opcode) of the next instruction (due to CPU pipeline) Note: The XC800 CPU fetches the opcode of the next instruction while executing the current instruction. Even with one wait state inserted for each byte of operand/opcode fetched, the XC800 CPU executes instructions faster than the standard 8051 processor by a factor of between two (e.g., 2-byte, 1-cycle instructions) to six (e.g., 1-byte, 4-cycle instructions).

  • Page 43: Accessing External Memory

    XC800 CPU Timing Accessing External Memory There are two types of external memory accesses: accesses to external program memory and accesses to external data memory. Accesses to external program memory use the signal PSEN as the read strobe, while accesses to external data memory use the RD or WR to read or write the memory.

  • Page 44: Accessing External Data Memory

    XC800 CPU Timing 3.2.2 Accessing External Data Memory External data memory may generally be accessed only if the corresponding address is not occupied by internal program memory in the code space. The access to external data memory uses address bits 17 up to 20 (if available) for bank selection.
  • Page 45 XC800 CPU Timing In a write cycle, the data byte to be written appears at the pins before WR is activated, and remains there after WR is deactivated. Figure 3-4 shows the timing of the external data memory write cycle. This timing assumes multiplexed program fetch and data access on the external interface.

  • Page 46: Instruction Set

    Instruction Set Instruction Set The XC800 8-bit microcontroller family instruction set includes the 111 instructions of the standard 8051, plus 2 additional instructions, MOVC @(DPTR++),A and TRAP, which are multiplexed and selected through the Special Function Register (SFR) EO. Out of the 113 instructions, 51 are single-byte, 46 are two-byte and 16 are three-byte.
  • Page 47 XC800 Instruction Set Direct Addressing Direct addressing is the only method of accessing the SFRs. The lower 128 bytes of internal RAM are also directly addressable. In direct addressing, the operand is specified by an 8-bit address field. Immediate Addressing Immediate addressing allows constants to be part of the instruction in program memory.

  • Page 48: Introduction To The Instruction Set

    Arithmetic can also be performed directly on packed BCD representations. Logic Instructions The XC800 microcontrollers perform basic logic operations on both bit and byte operands: ANL, ORL, SRL, CLR, SETB, CPL, RL, RLC, RR, RRC, SWAP. Data Transfer Instructions Data transfer operations are divided into three classes: •...
  • Page 49 XC800 Instruction Set Unconditional jumps transfer control from the current value of the program counter to the target address. These instructions are: AJMP, LJMP, SJMP and JMP @A + DPTR. Conditional jumps perform a jump contingent upon a specific condition. The destination will be within a 256-byte range centered about the starting address of the next instruction (–...

  • Page 50: Instructions

    XC800 Instruction Set Instructions The XC800 instructions can essentially be condensed to 55 basic operations. These operations are described in detail in the following sections. 4.3.1 Affected Flags Some instructions affect one or more of the PSW flags, as generally shown in Table 4-2.

  • Page 51: Instruction Table

    Instruction Table Table 4-3 lists all the instructions supported by XC800. Instructions are 1, 2 or 3 bytes long as indicated in the ‘Bytes’ column. Each instruction takes 1, 2 or 4 machine cycles to execute (with no wait state). One machine cycle comprises 2 CCLK clock cycles.
  • Page 52 XC800 Instruction Set Table 4-3 Instruction Table (cont’d) Mnemonic Description Hex Code Bytes Cycles INC DPTR Increment data pointer MUL AB Multiply A by B DIV AB Divide A by B DA A Decimal Adjust A LOGICAL ANL A,Rn AND register to A...
  • Page 53 XC800 Instruction Set Table 4-3 Instruction Table (cont’d) Mnemonic Description Hex Code Bytes Cycles RRC A Rotate A right through carry DATA TRANSFER MOV A,Rn Move register to A E8-EF MOV A,direct Move direct byte to A MOV A,@Ri Move indirect memory to A...
  • Page 54 XC800 Instruction Set Table 4-3 Instruction Table (cont’d) Mnemonic Description Hex Code Bytes Cycles XCH A,direct Exchange A and direct byte XCH A,@Ri Exchange A and indirect memory C6-C7 XCHD A,@Ri Exchange A and indirect memory D6-D7 nibble BOOLEAN CLR C...
  • Page 55 DJNZ direct,rel Decrement direct memory and jump relative if not zero MISCELLANEOUS No operation ADDITIONAL INSTRUCTIONS (selected through EO[7:4]) MOVC XC800-specific instruction for @(DPTR++),A software download into program memory: Copy from accumulator, then increment DPTR TRAP XC800-specific software break command User’s Manual, V 0.1...

  • Page 56: Instruction Definitions

    XC800 Instruction Set Notes on Data Addressing Modes: Working register R0-R7 direct 128 internal RAM locations, special function registers Indirect internal or external RAM location addressed by register R0 or R1 #data 8-bit constant included in instruction #data16 16-bit constant included in instruction...
  • Page 57 XC800 Instruction Set ACALL addr11 Function: Absolute call Description: ACALL unconditionally calls a subroutine located at the indicated address. The instruction increments the PC twice to obtain the address of the following instruction, then pushes the 16-bit result onto the stack (low-order byte first) and increments the stack pointer twice.
  • Page 58 XC800 Instruction Set A, <src-byte> Function: Description: ADD adds the byte variable indicated to the accumulator, leaving the result in the accumulator. The carry and auxiliary carry flags are set, respectively, if there is a carry out of bit 7 or bit 3, and cleared otherwise. When adding unsigned integers, the carry flag indicates an overflow occurred.
  • Page 59 XC800 Instruction Set A, @Ri Operation: (A) + ((Ri)) Encoding: 0 0 1 0 0 1 1 i Bytes: Cycles: A, #data Operation: (A) + #data Encoding: 0 0 1 0 0 1 0 0 immediate data Bytes: Cycles: User’s Manual, V 0.1...
  • Page 60 XC800 Instruction Set ADDC A, < src-byte> Function: Add with carry Description: ADDC simultaneously adds the byte variable indicated, the carry flag and the accumulator contents, leaving the result in the accumulator. The carry and auxiliary carry flags are set, respectively, if there is a carry out of bit 7 or bit 3, and cleared otherwise.
  • Page 61 XC800 Instruction Set ADDC A, @Ri Operation: ADDC (A) + (C) + ((Ri)) Encoding: 0 0 1 1 0 1 1 i Bytes: Cycles: ADDC A, #data Operation: ADDC (A) + (C) + #data Encoding: 0 0 1 1 0 1 0 0...
  • Page 62 XC800 Instruction Set AJMP addr11 Function: Absolute jump Description: AJMP transfers program execution to the indicated address, which is formed at run- time by concatenating the high-order five bits of the PC (after incrementing the PC twice), opcode bits 7-5, and the second byte of the instruction. The destination must therefore be within the same 2-Kbyte block of program memory as the first byte of the instruction following AJMP.
  • Page 63 XC800 Instruction Set <dest-byte>, <src-byte> Function: Logical AND for byte variables Description: ANL performs the bitwise logical AND operation between the variables indicated and stores the results in the destination variable. No flags are affected (except P, if <dest-byte> = A).
  • Page 64 XC800 Instruction Set A, @Ri Operation: ((Ri)) Encoding: 0 1 0 1 0 1 1 i Bytes: Cycles: A, #data Operation: #data Encoding: 0 1 0 1 0 1 0 0 immediate data Bytes: Cycles: direct,A Operation: (direct) (direct) Encoding:...
  • Page 65 XC800 Instruction Set direct, #data Operation: (direct) (direct) #data Encoding: 0 1 0 1 0 0 1 1 direct address immediate data Bytes: Cycles: User’s Manual, V 0.1 4-20 2005-01...
  • Page 66 XC800 Instruction Set C, <src-bit> Function: Logical AND for bit variables Description: If the Boolean value of the source bit is a logic 0 then clear the carry flag; otherwise leave the carry flag in its current state. A slash (“/”) preceding the operand in the assembly language indicates that the logical complement of the addressed bit is used as the source value, but the source bit itself is not affected.
  • Page 67 XC800 Instruction Set CJNE <dest-byte >, < src-byte >, rel Function: Compare and jump if not equal Description: CJNE compares the magnitudes of the first two operands, and branches if their values are not equal. The branch destination is computed by adding the signed relative displacement in the last instruction byte to the PC, after incrementing the PC to the start of the next instruction.
  • Page 68 XC800 Instruction Set CJNE A,direct,rel Operation: (PC) (PC) + 3 if (A) < > (direct) then (PC) (PC) + relative offset if (A) < (direct) then (C) 1 else (C) Encoding: 1 0 1 1 0 1 0 1 direct address rel.
  • Page 69 XC800 Instruction Set CJNE @Ri, #data, rel Operation: (PC) (PC) + 3 if ((Ri)) < > data then (PC) (PC) + relative offset if ((Ri)) < data then (C) else (C) Encoding: 1 0 1 1 0 1 1 i immediate data rel.
  • Page 70 XC800 Instruction Set Function: Clear accumulator Description: The accumulator is cleared (all bits set to zero). No flags are affected. Example: The accumulator contains 5C H (01011100 B ). The instruction will leave the accumulator set to 00 H (00000000 B ).
  • Page 71 XC800 Instruction Set Function: Clear bit Description: The indicated bit is cleared (reset to zero). No other flags are affected. CLR can operate on the carry flag or any directly addressable bit. Example: Port 1 has previously been written with 5D H (01011101 B ). The instruction P1.2...
  • Page 72 XC800 Instruction Set Function: Complement accumulator Description: Each bit of the accumulator is logically complemented (ones complement). Bits that previously contained a one are changed to zero and vice versa. No flags are affected. Example: The accumulator contains 5C H (01011100 B ). The instruction will leave the accumulator set to 0A3 H (10100011 B ).
  • Page 73 XC800 Instruction Set Function: Complement bit Description: The bit variable specified is complemented. A bit that had been a one is changed to zero and vice versa. No other flags are affected. CPL can operate on the carry or any directly addressable bit.
  • Page 74 XC800 Instruction Set Function: Decimal adjust accumulator for addition Description: DA A adjusts the eight-bit value in the accumulator resulting from the earlier addition of two variables (each in packed BCD format), producing two four-bit digits. Any ADD or ADDC instruction may have been used to perform the addition.
  • Page 75 XC800 Instruction Set BCD variables can be incremented or decremented by adding 01 H or 99 H . If the accumulator initially holds 30 H (representing the digits of 30 decimal), then the instruction sequence A, #99H will leave the carry set and 29 H in the accumulator, since 30 + 99 = 129. The low- order byte of the sum can be interpreted to mean 30 –...
  • Page 76 XC800 Instruction Set byte Function: Decrement Description: The variable indicated is decremented by 1. An original value of 00 H will underflow to 0FF H . No flags are affected. Four operand addressing modes are allowed: accumulator, register, direct, or register-indirect.
  • Page 77 XC800 Instruction Set direct Operation: (direct) (direct) – 1 Encoding: 0 0 0 1 0 1 0 1 direct address Bytes: Cycles: Operation: ((Ri)) ((Ri)) – 1 Encoding: 0 0 0 1 0 1 1 i Bytes: Cycles: User’s Manual, V 0.1...
  • Page 78 XC800 Instruction Set Function: Divide Description: DIV AB divides the unsigned eight-bit integer in the accumulator by the unsigned eight-bit integer in register B. The accumulator receives the integer part of the quotient; register B receives the integer remainder. The carry and OV flags will be cleared.
  • Page 79 XC800 Instruction Set DJNZ <byte>, <rel-addr> Function: Decrement and jump if not zero Description: DJNZ decrements the location indicated by 1, and branches to the address indicated by the second operand if the resulting value is not zero. An original value of 00 H will underflow to 0FF H .
  • Page 80 XC800 Instruction Set DJNZ Rn,rel Operation: DJNZ (PC) (PC) + 2 (Rn) (Rn) – 1 if (Rn) > 0 or (Rn) < 0 then (PC) (PC) + rel Encoding: 1 1 0 1 1 r r r rel. address Bytes:...
  • Page 81 XC800 Instruction Set <byte> Function: Increment Description: INC increments the indicated variable by 1. An original value of 0FF H will overflow to 00 H . No flags are affected. Three addressing modes are allowed: register, direct, or register-indirect. Note: When this instruction is used to modify an output port, the value used as the original port data will be read from the output data latch, not the input pins.
  • Page 82 XC800 Instruction Set direct Operation: (direct) (direct) + 1 Encoding: 0 0 0 0 0 1 0 1 direct address Bytes: Cycles: Operation: ((Ri)) ((Ri)) + 1 Encoding: 0 0 0 0 0 1 1 i Bytes: Cycles: User’s Manual, V 0.1...
  • Page 83 XC800 Instruction Set DPTR Function: Increment data pointer Description: Increment the 16-bit data pointer by 1. A 16-bit increment (modulo 2 ) is performed; an overflow of the low-order byte of the data pointer (DPL) from 0FF H to 00 H will increment the high-order byte (DPH).
  • Page 84 XC800 Instruction Set bit,rel Function: Jump if bit is set Description: If the indicated bit is a one, jump to the address indicated; otherwise proceed with the next instruction. The branch destination is computed by adding the signed relative-displacement in the third instruction byte to the PC, after incrementing the PC to the first byte of the next instruction.
  • Page 85 XC800 Instruction Set bit,rel Function: Jump if bit is set and clear bit Description: If the indicated bit is one, branch to the address indicated; otherwise proceed with the next instruction. In either case, clear the designated bit. The branch destination is computed by adding the signed relative displacement in the third instruction byte to the PC, after incrementing the PC to the first byte of the next instruction.
  • Page 86 XC800 Instruction Set Function: Jump if carry is set Description: If the carry flag is set, branch to the address indicated; otherwise proceed with the next instruction. The branch destination is computed by adding the signed relative- displacement in the second instruction byte to the PC, after incrementing the PC twice.
  • Page 87 XC800 Instruction Set @A + DPTR Function: Jump indirect Description: Add the eight-bit unsigned contents of the accumulator with the sixteen-bit data pointer, and load the resulting sum to the program counter. This will be the address for subsequent instruction fetches. Sixteen-bit addition is performed (modulo 2 ): a carry-out from the low-order eight bits propagates through the higher-order bits.
  • Page 88 XC800 Instruction Set bit,rel Function: Jump if bit is not set Description: If the indicated bit is a zero, branch to the indicated address; otherwise proceed with the next instruction. The branch destination is computed by adding the signed relative-displacement in the third instruction byte to the PC, after incrementing the PC to the first byte of the next instruction.
  • Page 89 XC800 Instruction Set Function: Jump if carry is not set Description: If the carry flag is a zero, branch to the address indicated; otherwise proceed with the next instruction. The branch destination is computed by adding the signed relative-displacement in the second instruction byte to the PC, after incrementing the PC twice to point to the next instruction.
  • Page 90 XC800 Instruction Set Function: Jump if accumulator is not zero Description: If any bit of the accumulator is a one, branch to the indicated address; otherwise proceed with the next instruction. The branch destination is computed by adding the signed relative-displacement in the second instruction byte to the PC, after incrementing the PC twice.
  • Page 91 XC800 Instruction Set Function: Jump if accumulator is zero Description: If all bits of the accumulator are zero, branch to the address indicated; otherwise proceed with the next instruction. The branch destination is computed by adding the signed relative-displacement in the second instruction byte to the PC, after incrementing the PC twice.
  • Page 92 XC800 Instruction Set LCALL addr16 Function: Long call Description: LCALL calls a subroutine located at the indicated address. The instruction adds three to the program counter to generate the address of the next instruction and then pushes the 16-bit result onto the stack (low byte first), incrementing the stack pointer by two.
  • Page 93 XC800 Instruction Set LJMP addr16 Function: Long jump Description: LJMP causes an unconditional branch to the indicated address, by loading the high- order and low-order bytes of the PC (respectively) with the second and third instruction bytes. The destination may therefore be anywhere in the full 64-Kbyte program memory address space.
  • Page 94 XC800 Instruction Set <dest-byte>, <src-byte> Function: Move byte variable Description: The byte variable indicated by the second operand is copied into the location specified by the first operand. The source byte is not affected. No other register or flag is affected.
  • Page 95 XC800 Instruction Set A,@Ri Operation: ((Ri)) Encoding: 1 1 1 0 0 1 1 i Bytes: Cycles: A, #data Operation: #data Encoding: 0 1 1 1 0 1 0 0 immediate data Bytes: Cycles: Rn,A Operation: (Rn) Encoding: 1 1 1 1...
  • Page 96 XC800 Instruction Set Rn, #data Operation: (Rn) #data Encoding: 0 1 1 1 1 r r r immediate data Bytes: Cycles: direct,A Operation: (direct) Encoding: 1 1 1 1 0 1 0 1 direct address Bytes: Cycles: direct,Rn Operation: (direct)
  • Page 97 XC800 Instruction Set direct, @ Ri Operation: (direct) ((Ri)) Encoding: 1 0 0 0 0 1 1 i direct address Bytes: Cycles: direct, #data Operation: (direct) #data Encoding: 0 1 1 1 0 1 0 1 direct address immediate data...
  • Page 98 XC800 Instruction Set @ Ri,#data Operation: ((Ri)) #data Encoding: 0 1 1 1 0 1 1 i immediate data Bytes: Cycles: User’s Manual, V 0.1 4-53 2005-01...
  • Page 99 XC800 Instruction Set <dest-bit>, <src-bit> Function: Move bit data Description: The Boolean variable indicated by the second operand is copied into the location specified by the first operand. One of the operands must be the carry flag; the other may be any directly addressable bit. No other register or flag is affected.
  • Page 100 XC800 Instruction Set DPTR, #data16 Function: Load data pointer with a 16-bit constant Description: The data pointer is loaded with the 16-bit constant indicated. The 16-bit constant is loaded into the second and third bytes of the instruction. The second byte (DPH) is the high-order byte, while the third byte (DPL) holds the low-order byte.
  • Page 101 XC800 Instruction Set MOVC A, @A + <base-reg> Function: Read code byte Description: Load the accumulator with a code byte, or constant from program memory. The address of the byte fetched is the sum of the original unsigned eight-bit accumulator contents and the contents of a sixteen-bit base register, which may be either the data pointer or the PC.
  • Page 102 XC800 Instruction Set MOVC A, @A + PC Operation: MOVC (PC) (PC) + 1 ((A) + (PC)) Encoding: 1 0 0 0 0 0 1 1 Bytes: Cycles: User’s Manual, V 0.1 4-57 2005-01...
  • Page 103 0 1 0 1 Bytes: Cycles: Note: This instruction is XC800-specific, therefore may not be supported by standard 8051 assembler. In such cases, this can be workaround by direct byte declaration and definition e.g. “.byte #A5 ” (syntax is assembler dependent).
  • Page 104 XC800 Instruction Set MOVX <dest-byte>, <src-byte> Function: Move external Description: The MOVX instructions transfer data between the accumulator and a byte of external data memory, hence the “X” appended to MOV. There are two types of instructions, differing in whether they provide an 8-bit or 16-bit indirect address to the external data RAM.
  • Page 105 XC800 Instruction Set MOVX A,@Ri Operation: MOVX ((Ri)) Encoding: 1 1 1 0 0 0 1 i Bytes: Cycles: MOVX A,@DPTR Operation: MOVX ((DPTR)) Encoding: 1 1 1 0 0 0 0 0 Bytes: Cycles: MOVX @Ri,A Operation: MOVX ((Ri))
  • Page 106 XC800 Instruction Set Function: Multiply Description: MUL AB multiplies the unsigned eight-bit integers in the accumulator and register B. The low-order byte of the sixteen-bit product is left in the accumulator, and the high-order byte in B. If the product is greater than 255 (0FF H ) the overflow flag is set;...
  • Page 107 XC800 Instruction Set Function: No operation Description: Execution continues at the following instruction. Other than the PC, no registers or flags are affected. Example: It is desired to produce a low-going output pulse on bit 7 of port 2 lasting exactly 5 cycles.
  • Page 108 XC800 Instruction Set <dest-byte>, <src-byte> Function: Logical OR for byte variables Description: ORL performs the bitwise logical OR operation between the indicated variables, storing the results in the destination byte. No flags are affected (except P, if <dest-byte> = A).
  • Page 109 XC800 Instruction Set A,direct Operation: (direct) Encoding: 0 1 0 0 0 1 0 1 direct address Bytes: Cycles: A,@Ri Operation: ((Ri)) Encoding: 0 1 0 0 0 1 1 i Bytes: Cycles: A,#data Operation: #data Encoding: 0 1 0 0...
  • Page 110 XC800 Instruction Set direct, #data Operation: (direct) (direct) #data Encoding: 0 1 0 0 0 0 1 1 direct address immediate data Bytes: Cycles: User’s Manual, V 0.1 4-65 2005-01...
  • Page 111 XC800 Instruction Set C, <src-bit> Function: Logical OR for bit variables Description: Set the carry flag if the Boolean value is a logic 1; leave the carry in its current state otherwise. A slash (“/”) preceding the operand in the assembly language indicates that the logical complement of the addressed bit is used as the source value, but the source bit itself is not affected.
  • Page 112 XC800 Instruction Set direct Function: Pop from stack Description: The contents of the internal RAM location addressed by the stack pointer is read, and the stack pointer is decremented by one. The value read is the transfer to the directly addressed byte indicated. No flags are affected.
  • Page 113 XC800 Instruction Set PUSH direct Function: Push onto stack Description: The stack pointer is incremented by one. The content of the indicated variable is then copied into the internal RAM location addressed by the stack pointer. Otherwise no flags are affected.
  • Page 114 XC800 Instruction Set Function: Return from subroutine Description: RET pops the high and low-order bytes of the PC successively from the stack, decrementing the stack pointer by two. Program execution continues at the resulting address, generally the instruction immediately following an ACALL or LCALL.
  • Page 115 XC800 Instruction Set RETI Function: Return from interrupt Description: RETI pops the high and low-order bytes of the PC successively from the stack, and restores the interrupt logic to accept additional interrupts at the same priority level as the one just processed. The stack pointer is left decremented by two. No other registers are affected;...
  • Page 116 XC800 Instruction Set Function: Rotate accumulator left Description: The eight bits in the accumulator are rotated one bit to the left. Bit 7 is rotated into the bit 0 position. No flags are affected. Example: The accumulator holds the value 0C5 H (11000101 B ). The instruction leaves the accumulator holding the value 8B H (10001011 B ) with the carry unaffected.
  • Page 117 XC800 Instruction Set Function: Rotate accumulator left through carry flag Description: The eight bits in the accumulator and the carry flag are together rotated one bit to the left. Bit 7 moves into the carry flag; the original state of the carry flag moves into the bit 0 position.
  • Page 118 XC800 Instruction Set Function: Rotate accumulator right Description: The eight bits in the accumulator are rotated one bit to the right. Bit 0 is rotated into the bit 7 position. No flags are affected. Example: The accumulator holds the value 0C5 H (11000101 B ). The instruction leaves the accumulator holding the value 0E2 H (11100010 B ) with the carry unaffected.
  • Page 119 XC800 Instruction Set Function: Rotate accumulator right through carry flag Description: The eight bits in the accumulator and the carry flag are together rotated one bit to the right. Bit 0 moves into the carry flag; the original value of the carry flag moves into the bit 7 position.
  • Page 120 XC800 Instruction Set SETB <bit> Function: Set bit Description: SETB sets the indicated bit to one. SETB can operate on the carry flag or any directiy addressable bit. No other flags are affected. Example: The carry flag is cleared. Output port 1 has been written with the value 34 H (00110100 B ).
  • Page 121 XC800 Instruction Set SJMP Function: Short jump Description: Program control branches unconditionally to the address indicated. The branch destination is computed by adding the signed displacement in the second instruction byte to the PC, after incrementing the PC twice. Therefore, the range of destinations allowed is from 128 bytes preceding this instruction to 127 bytes following it.
  • Page 122 XC800 Instruction Set SUBB A, <src-byte> Function: Subtract with borrow Description: SUBB subtracts the indicated variable and the carry flag together from the accumulator, leaving the result in the accumulator. SUBB sets the carry (borrow) flag if a borrow is needed for bit 7, and clears C otherwise. (If C was set before...
  • Page 123 XC800 Instruction Set SUBB A,direct Operation: SUBB (A) – (C) – (direct) Encoding: 1 0 0 1 0 1 0 1 direct address Bytes: Cycles: SUBB A, @ Ri Operation: SUBB (A) – (C) – ((Ri)) Encoding: 1 0 0 1...
  • Page 124 XC800 Instruction Set SWAP Function: Swap nibbles within the accumulator Description: SWAP A interchanges the low and high-order nibbles (four-bit fields) of the accumulator (bits 3-0 and bits 7-4). The operation can also be thought of as a four- bit rotate instruction. No flags are affected.
  • Page 125 0 1 0 1 Bytes: Cycles: Note: This instruction is XC800-specific, therefore may not be supported by standard 8051 assembler. In such cases, this can be workaround by direct byte declaration and definition e.g. “.byte #A5 ” (syntax is assembler dependent).
  • Page 126 XC800 Instruction Set A, <byte> Function: Exchange accumulator with byte variable Description: XCH loads the accumulator with the contents of the indicated variable, at the same time writing the original accumulator contents to the indicated variable. The source/ destination operand can use register, direct, or register-indirect addressing.
  • Page 127 XC800 Instruction Set A, @ Ri Operation: ((Ri)) Encoding: 1 1 0 0 0 1 1 i Bytes: Cycles: User’s Manual, V 0.1 4-82 2005-01...
  • Page 128 XC800 Instruction Set XCHD A,@Ri Function: Exchange digit Description: XCHD exchanges the low-order nibble of the accumulator (bits 3-0, generally representing a hexadecimal or BCD digit), with that of the internal RAM location indirectly addressed by the specified register. The high-order nibbles (bits 7-4) of each register are not affected.
  • Page 129 XC800 Instruction Set <dest-byte>, <src-byte> Function: Logical Exclusive OR for byte variables Description: XRL performs the bitwise logical Exclusive OR operation between the indicated variables, storing the results in the destination. No flags are affected (except P, if <dest-byte> = A).
  • Page 130 XC800 Instruction Set A,direct Operation: (direct) Encoding: 0 1 1 0 0 1 0 1 direct address Bytes: Cycles: A, @ Ri Operation: ((Ri)) Encoding: 0 1 1 0 0 1 1 i Bytes: Cycles: A, #data Operation: #data Encoding:...
  • Page 131 XC800 Instruction Set direct, #data Operation: (direct) (direct) #data Encoding: 0 1 1 0 0 0 1 1 direct address immediate data Bytes: Cycles: User’s Manual, V 0.1 4-86 2005-01...
  • Page 132 . i n f i n e o n . c o m Published by Infineon Technologies AG...

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