Exiting An Interrupt Service Routine - Infineon Technologies TC1728 User Manual

As explained, receipt of further interrupts is disabled (ICR.IE = 0) when an Interrupt
Service Routine is entered. At the same time, the current CPU priority ICR.CCPN is set
by hardware to the priority of the interrupting source (ICR.PIPN).
Clearly, before the processor can receive any more interrupts, the ISR must eventually
re-enable the interrupt system again by setting ICR.IE = 1. Furthermore, the ISR can
also modify the priority number ICR.CCPN to allow effective interrupt priority levels. It is
up to the user to enable the interrupt system again and optionally modify the priority
number CCPN to implement interrupt priority levels or handle special cases.
To simply enable the interrupt system again, the ENABLE instruction can be used, which
sets ICR.IE bit to 1. The BISR instruction offers a convenient way to re-enable the
interrupt system, to set ICR.CCPN to a new value, and to save the lower context of the
interrupted task. It is also possible to use an MTCR instruction to modify ICR.IE and
ICR.CCPN. However, this should be performed together with an ISYNC instruction
(which synchronizes the instruction stream) to ensure completion of this operation before
the execution of following instructions.
Note: The lower context can also be saved through execution of an SVLCX (Save Lower
Context) instruction.
13.6

Exiting an Interrupt Service Routine

When an ISR exits with an RFE (Return From Exception) instruction, the hardware
automatically restores the upper context. Register PCXI, which holds the Previous CPU
Priority Number (PCPN) and the Previous Global Interrupt Enable Bit (PIE), is a part of
this upper context. The value saved in PCPN is written to ICR.CCPN to set the CPU
priority number to the value before the interruption, and bit PIE is written to ICR.IE to
restore the state of this bit. The interrupted routine then continues.
Note: There is no automatic restoring of the lower context on an exit from an Interrupt
Service Routine. If the lower context was saved during the execution of the ISR,
either through execution of the BISR instruction or an SVLCX instruction, the ISR
must restore the lower context again via the RSLCX (Restore Lower Context)
instruction before it exits through RFI execution.
User's Manual
Interrupt, V1.4
13-14
TC1728
Interrupt System
V1.0, 2011-12